ICS9112-06中文资料ICST数据手册PDF规格书

General Description

The ICS9112 is a high performance, low skew, low jitter clock driver. It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the REF input with the CLKOUT signal. It is designed to distribute high speed clocks in PC systems operating at speeds from 25 to 75 MHz (30 to 90mHz for 5V operation).

Features

• Zero input - output delay

• Frequency range 25 - 75 MHz (3.3V), 30-90MHz (5.0V)

• Less than 200 ps Jitter between outputs

• Skew controlled outputs

• Skew less than 250 ps between outputs

• Available in 8 or 16 pin versions, 150 mil SOIC packages

• 3.3V ±10, 5.0V±10 operation