1:5 Differential-to-LVDS Zero Delay Clock Generator

Features • Five differential LVDS outputs designed to meet or exceed the requirements of ANSI TIA/EIA-644 • Selectable differential clock inputs • CLKx, nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Output frequency range: 31.25MHz to 700M

文件：880.85 Kbytes 页数：21 Pages

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1:5 Differential-to-LVDS Zero Delay Clock Generator

文件：814.38 Kbytes 页数：20 Pages

IDT

Output frequency range

文件：898.32 Kbytes 页数：21 Pages

IDT

Output frequency range

Renesas

瑞萨