-2.5V/ 3.3V LVPECL CLOCK GENERATOR

文件：128.449 Kbytes 页数：10 Pages

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Differential-to-3.3V LVPECL Clock Generator

文件：198.44 Kbytes 页数：15 Pages

IDT

÷4/÷5 Differential-to-3.3V LVPECL Clock Generator

FEATURES • One differential 3.3V LVPECL output • One CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Maximum clock input frequency: 1GHz • Translates any single ended input signal (LVCMOS, LVTTL, GTL) to LVPECL lev

文件：359.17 Kbytes 页数：16 Pages

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瑞萨

Differential-to-3.3V LVPECL Clock Generator

文件：198.44 Kbytes 页数：15 Pages

IDT