丝印：ICS8516FYI；Package：LQFP；Low Skew, 1-to-16 Differential-to- LVDS, Clock Distribution Chip

FEATURES • Sixteen Differential LVDS outputs • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Maximum output frequency: 700MHz • Translates any differential input signal (LVPECL, LVHSTL, SSTL, DCM) to LVDS levels without external bias ne

文件：599.05 Kbytes 页数：19 Pages

RENESAS

瑞萨

丝印：ICS8516FYI；Package：LQFP；Low Skew, 1-to-16 Differential-to- LVDS, Clock Distribution Chip

FEATURES • Sixteen Differential LVDS outputs • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Maximum output frequency: 700MHz • Translates any differential input signal (LVPECL, LVHSTL, SSTL, DCM) to LVDS levels without external bias ne

文件：599.05 Kbytes 页数：19 Pages

RENESAS

瑞萨

丝印：ICS8516FYI；Package：LQFP；Low Skew, 1-to-16 Differential-to-LVDS, Clock Distribution Chip

文件：181.32 Kbytes 页数：18 Pages

IDT

丝印：ICS8516FYI；Package：LQFP；Low Skew, 1-to-16 Differential-to-LVDS, Clock Distribution Chip

文件：181.32 Kbytes 页数：18 Pages

IDT

丝印：ICS8516FYILF；Package：LQFP；Low Skew, 1-to-16 Differential-to- LVDS, Clock Distribution Chip

FEATURES • Sixteen Differential LVDS outputs • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Maximum output frequency: 700MHz • Translates any differential input signal (LVPECL, LVHSTL, SSTL, DCM) to LVDS levels without external bias ne

文件：599.05 Kbytes 页数：19 Pages

RENESAS

瑞萨

丝印：ICS8516FYILF；Package：LQFP；Low Skew, 1-to-16 Differential-to- LVDS, Clock Distribution Chip

FEATURES • Sixteen Differential LVDS outputs • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Maximum output frequency: 700MHz • Translates any differential input signal (LVPECL, LVHSTL, SSTL, DCM) to LVDS levels without external bias ne

文件：599.05 Kbytes 页数：19 Pages

RENESAS

瑞萨

丝印：ICS8516FYILF；Package：LQFP；Low Skew, 1-to-16 Differential-to-LVDS, Clock Distribution Chip

文件：181.32 Kbytes 页数：18 Pages

IDT

丝印：ICS8516FYILF；Package：LQFP；Low Skew, 1-to-16 Differential-to-LVDS, Clock Distribution Chip

文件：181.32 Kbytes 页数：18 Pages

IDT

LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP

GENERALDESCRIPTION The ICS8516I is a low skew, high performance 1-to-16 Differential-to-LVDS Clock Distribution Chip and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS8516I CLK, nCLK pair can accept any differential input levels and translates them to

文件：170.41 Kbytes 页数：13 Pages

ICST

LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP

GENERALDESCRIPTION The ICS8516I is a low skew, high performance 1-to-16 Differential-to-LVDS Clock Distribution Chip and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS8516I CLK, nCLK pair can accept any differential input levels and translates them to

文件：170.41 Kbytes 页数：13 Pages

ICST