丝印：ICS507M-01LF；Package：SOIC；PECL CLOCK SYNTHESIZER

Features • Packaged in 16 pin SOIC • Available in Pb (lead) free package • Input crystal frequency of 5 - 27 MHz • Input clock frequency of 5 - 52 MHz • Enable usage of common low-cost crystal • Differential PECL output clock frequencies up to 200 MHz • Duty cycle of 49/51 • Operation vol

文件：324.46 Kbytes 页数：8 Pages

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丝印：ICS507M-01LF；Package：SOIC；PECL CLOCK SYNTHESIZER

Features • Packaged in 16 pin SOIC • Available in Pb (lead) free package • Input crystal frequency of 5 - 27 MHz • Input clock frequency of 5 - 52 MHz • Enable usage of common low-cost crystal • Differential PECL output clock frequencies up to 200 MHz • Duty cycle of 49/51 • Operation vol

文件：324.46 Kbytes 页数：8 Pages

RENESAS

瑞萨

PECL Clock Synthesizer

Description The ICS507-01 and ICS507-02 are inexpensive ways to generate a low jitter 155.52 MHz (or other high speed) differential PECL clock output from a low frequency crystal input. Using Phase-Locked-Loop (PLL) techniques, the devices use a standard fundamental mode crystal to produce out

文件：49.61 Kbytes 页数：5 Pages

ICST

PECL CLOCK SYNTHESIZER

Features • Packaged in 16 pin SOIC • Available in Pb (lead) free package • Input crystal frequency of 5 - 27 MHz • Input clock frequency of 5 - 52 MHz • Enable usage of common low-cost crystal • Differential PECL output clock frequencies up to 200 MHz • Duty cycle of 49/51 • Operation vol

文件：324.46 Kbytes 页数：8 Pages

RENESAS

瑞萨

PECL CLOCK SYNTHESIZER

Features • Packaged in 16 pin SOIC • Available in Pb (lead) free package • Input crystal frequency of 5 - 27 MHz • Input clock frequency of 5 - 52 MHz • Enable usage of common low-cost crystal • Differential PECL output clock frequencies up to 200 MHz • Duty cycle of 49/51 • Operation vol

文件：324.46 Kbytes 页数：8 Pages

RENESAS

瑞萨

PECL CLOCK SYNTHESIZER

Features • Packaged in 16 pin SOIC • Available in Pb (lead) free package • Input crystal frequency of 5 - 27 MHz • Input clock frequency of 5 - 52 MHz • Enable usage of common low-cost crystal • Differential PECL output clock frequencies up to 200 MHz • Duty cycle of 49/51 • Operation vol

文件：324.46 Kbytes 页数：8 Pages

RENESAS

瑞萨