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I74F50729D中文资料飞利浦数据手册PDF规格书
I74F50729D规格书详情
DESCRIPTION
The 74F50729 is a dual positive edge–triggered D–type featuring individual data, clock, set and reset inputs; also true and complementary outputs.
The 74F50729 is designed so that the outputs can never display a metastable state due to setup and hold time violations. If setup time and hold time are violated the propagation delays may be extended beyond the specifications but the outputs will not glitch or display a metastable state. Typical metastability parameters for the 74F50729 are: τ ≅ 135ps and τ ≅ 9.8 X 106 sec where τ represents a function of the rate at which a latch in a metastable state resolves that condition and To represents a function of the measurement of the propensity of a latch to enter a metastable state.
FEATURES
• Metastable immune characteristics
• Output skew less than 1.5ns
• High source current (IOH = 15mA) ideal for clock driver applications
• See 74F5074 for synchronizing dual D–type flip–flop
• See 74F50109 for synchronizing dual J–K positive edge–triggered flip–flop
• See 74F50728 for synchronizing cascaded dual D–type flip–flop
• Industrial temperature range available (–40°C to +85°C)
产品属性
- 型号:
I74F50729D
- 制造商:
PHILIPS
- 制造商全称:
NXP Semiconductors
- 功能描述:
Synchronizing dual D-type flip-flop with edge-triggered set and reset with metastable immune characteristics
供应商 | 型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
---|---|---|---|---|---|---|---|
PHILIPS |
2020+ |
SOP16-3 |
80000 |
只做自己库存,全新原装进口正品假一赔百,可开13%增 |
询价 | ||
PHILIPS |
1815+ |
SOP14-3.9 |
6528 |
只做原装正品现货!或订货,假一赔十! |
询价 | ||
NXP |
21+ |
24SO |
13880 |
公司只售原装,支持实单 |
询价 | ||
PHILIPS/飞利浦 |
23+ |
NA/ |
5750 |
原装现货,当天可交货,原型号开票 |
询价 | ||
PHILIPS |
SOP14 |
68900 |
原包原标签100%进口原装常备现货! |
询价 | |||
PHILIPS/飞利浦 |
23+ |
SOP14 |
4000 |
一级代理原厂VIP渠道,专注军工、汽车、医疗、工业、 |
询价 | ||
PHI |
03+ |
SOP-7.2-24P |
250 |
询价 | |||
PHILIPS |
22+ |
SOP20 |
2650 |
原装优势!绝对公司现货 |
询价 | ||
NXP |
2024+ |
SOT137 |
188600 |
全新原厂原装正品现货 欢迎咨询 |
询价 | ||
NXP |
22+ |
24SO |
9000 |
原厂渠道,现货配单 |
询价 |