HM5264165F-B60

64M LVTTL interface SDRAM 133 MHz/100 MHz 1-Mword 횞 16-bit 횞 4-bank/2-Mword 횞 8-bit 횞 4-bank /4-Mword 횞 4-bit 횞 4-bank PC/133, PC/100 SDRAM

Description TheHM5264165Fisa64-MbitSDRAMorganizedas1048576-word×16-bit×4bank.TheHM5264805Fisa64-MbitSDRAMorganizedas2097152-word×8-bit×4bank.TheHM5264405Fisa64-MbitSDRAMorganizedas4194304-word×4-bit×4bank.Allinputsandoutputsarereferredtotherisin

HM5264165F-B60

64M LVTTL interface SDRAM 133 MHz/100 MHz; • 3.3 V power supply\n• Clock frequency: 133 MHz/100 MHz (max)\n• LVTTL interface\n• Single pulsed RAS\n• 4 banks can operate simultaneously and independently\n• Burst read/write operation and burst read/single write operation capability\n• Programmable burst length: 1/2/4/8/full page\n• 2 variations of burst sequence\n- Sequential (BL = 1/2/4/8/full page)\n- Interleave (BL = 1/2/4/8)\n• Programmable CAS latency: 2/3\n• Byte control by DQM:DQM (HM5264805F/HM5264405F) DQMU/DQML (HM5264165F)\n• Refresh cycles: 4096 refresh cycles/64 ms\n• 2 variations of refresh\n- Auto refresh\n- Self refresh\n• Full page burst length capability\n- Sequential burst\n- Burst stop capability;

1-Mword × 16-bit × 4-bank/2-Mword × 8-bit × 4-bank /4-Mword × 4-bit × 4-bank PC/133, PC/100 SDRAMDescription\nThe Hitachi HM5264165F is a 64-Mbit SDRAM organized as 1048576-word × 16-bit × 4 bank. The Hitachi HM5264805F is a 64-Mbit SDRAM organized as 2097152-word × 8-bit × 4 bank. The Hitachi HM5264405F is a 64-Mbit SDRAM organized as 4194304-word × 4-bit × 4 bank. All inputs and outputs are referred to the rising edge of the clock input. It is packaged in standard 54-pin plastic TSOP II.