1024 x 4 CMOS RAM

Description The HM-6514 is a 1024 x 4 static CMOS RAM fabricated using self-aligned silicon gate technology. The device utilizes synchronous circuitry to achieve high performance and low power operation. On-chip latches are provided for addresses allowing efficient interfacing with microproc

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1024 x 4 CMOS RAM

• This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. • Low Power Standby . . . . . . . . . . . . . . . . . . . 125W Max • Low Power Operation. . . . . . . . . . . . . . 35mW/MHz Max • Data Retention . . . . . . . . . . . . .

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1024 x 4 CMOS RAM

• This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. • Low Power Standby . . . . . . . . . . . . . . . . . . . 125W Max • Low Power Operation. . . . . . . . . . . . . . 35mW/MHz Max • Data Retention . . . . . . . . . . . . .

文件：348.02 Kbytes 页数：9 Pages

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1024 x 4 CMOS RAM

文件：193.57 Kbytes 页数：9 Pages

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1024 x 4 CMOS RAM

文件：193.57 Kbytes 页数：9 Pages

Intersil

1024 x 4 CMOS RAM

文件：193.57 Kbytes 页数：9 Pages

Intersil

1024x4 CMOS RAM

The HM-6514/883 is a 1024 x 4 static CMOS RAM fabricated using self-aligned silicon gate technology. The device utilizes synchronous circuitry to achieve high performance and low power operation. On chip latches are provided for addresses allowing efficient interfacing with microprocessor systems. T • This Circuit is Processed in Accordance to MIL-STD- 883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1.\n• Low Power Standby 125µW Max\n• Low Power Operation 35mW/MHz Max\n• Data Retention at 2.0V Min\n• TTL Compatible Input/Output\n• Common Data Input/Output\n• Three-State Output;

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