1. General description

The HEF4020B is a 14-stage binary ripple counter with a clock input (CP), an overriding

asynchronous master reset input (MR) and 12 buffered parallel outputs (Q0, and Q3 to Q13). The

counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages

and forces all outputs LOW, independent of the state of CP. Each counter stage is a static toggle

flip-flop. Inputs include clamp diodes. This enables the use of current limiting resistors to interface

inputs to voltages in excess of VDD.

2. Features and benefits

• Wide supply voltage range from 3.0 V to 15.0 V

• CMOS low power dissipation

• High noise immunity

• High speed operation

• Fully static operation

• 5 V, 10 V, and 15 V parametric ratings

• Standardized symmetrical output characteristics

• Complies with JEDEC standard JESD 13-B

• ESD protection:

• HBM JESD22-A114F exceeds 2000 V

• MM JESD22-A115-B exceeds 200 V

• Specified from -40 °C to +85 °C

HEF4020BT属于集成电路（IC） > 计数器，除法器。安世半导体(中国)有限公司制造生产的HEF4020BT计数器，除法器计数器和除法器 IC 是数字逻辑器件，可对输入发生的逻辑转换进行计数，然后使用多个并行输出重新发送累加的计数，和/或生成单个输出信号转换，从而对应用某些整数数量输入信号转换进行响应。除了简单的事件计数，它们还可用于各种频率合成应用。