Octal Transparent Latches (with 3-state outputs)

Description When the latch enable (LE) input is high, the Q outputs of HD74HC563 will follow the inversion of the D inputs and the Q outputs of HD74HC573 will follow the D inputs. When the latch enable goes low, data at the D inputs will be retained at the outputs until latch enable returns hig

文件：138.73 Kbytes 页数：11 Pages

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Octal Transparent Latches (with 3-state outputs)

文件：161.18 Kbytes 页数：13 Pages

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Octal Transparent Latches (with 3-state outputs)

Description When the latch enable (LE) input is high, the Q outputs of HD74HC563 will follow the inversion of the D inputs and the Q outputs of HD74HC573 will follow the D inputs. When the latch enable goes low, data at the D inputs will be retained at the outputs until latch enable returns hig

文件：138.73 Kbytes 页数：11 Pages

RENESAS

瑞萨

Octal Transparent Latches (with 3-state outputs)

文件：161.18 Kbytes 页数：13 Pages

RENESAS

瑞萨

OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT HC563 INVERTING - HC573 NON INVERTING

DESCRIPTION The M54/74HC563 and M54HC573 are high speed CMOS OCTAL LATCH WITH 3-STATE OUTPUTS fabricated with in silicon gate C2MOS technology. These ICs archive the high speed operation similar to equivalent LSTTL while maintaning the CMOS low power dissipation. ■ HIGH SPEED tPD = 13 ns (T

文件：273.55 Kbytes 页数：13 Pages

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