Phase-Locked Loop Clock Distribution for Synchronous DRAM Applications

General Description The HC2509C is a low-skew, low jitter, phase-locked loop(PLL) clock driver, distributing high frequency clock signals for SDRAM. Features ● Phase-Locked Loop Clock Distribution for Synchronous DRAM Applications ● Supports PC-100 and Meets “PC100 SDRAM registered DIMM Specif

文件：84 Kbytes 页数：6 Pages

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Phase-Locked Loop Clock Distribution for Synchronous DRAM Applications

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海力士

3.3V Phase-Lock Loop Clock Driver

General Description The ICS2509C is a high performance, low skew, low jitter clock driver. It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the CLKIN signal with the CLKOUT signal. It is specifically designed for use with synchronous SDRAMs. The ICS2509C operates

文件：248.21 Kbytes 页数：7 Pages

ICST

3.3V Phase-Lock Loop Clock Driver

General Description The ICS2509C is a high performance, low skew, low jitter clock driver. It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the CLKIN signal with the CLKOUT signal. It is specifically designed for use with synchronous SDRAMs. The ICS2509C operates

文件：248.21 Kbytes 页数：7 Pages

ICST

3.3V Phase-Lock Loop Clock Driver

General Description The ICS2509C is a high performance, low skew, low jitter clock driver. It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the CLKIN signal with the CLKOUT signal. It is specifically designed for use with synchronous SDRAMs. The ICS2509C operates

文件：248.21 Kbytes 页数：7 Pages

ICST