HC125中文资料飞利浦数据手册PDF规格书

DESCRIPTION

The 74AHC/AHCT125 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A.

The 74AHC/AHCT125 are four non-inverting buffer/line drivers with 3-state outputs. The 3-state outputs (nY) are controlled by the output enable input (nOE). A HIGH at n causes the outputs to assume a HIGH-impedance OFF-state.

The ‘125’ is identical to the ‘126’ but has active LOW enable inputs.

FEATURES

• ESD protection:

HBM EIA/JESD22-A114-A

exceeds 2000 V

MM EIA/JESD22-A115-A

exceeds 200 V

CDM EIA/JESD22-C101

exceeds 1000 V

• Balanced propagation delays

• All inputs have Schmitt-trigger actions

• Inputs accepts voltages higher than VCC

• For AHC only: operates with CMOS input levels

• For AHCT only: operates with TTL input levels

• Specified from −40 to +85 and +125 °C.