GPL95101UA数据手册Generalplus中文资料规格书

描述 Description

GPL95101UA, a highly integrated System-on-a-Chip (SoC), is a cost-effective and high performance micro-controller solution for game, education and interactive learning applications.  It equips a m’nSP® 2.0 CPU with 8KB I-cache, picture process unit (PPU),  16-channel sound process unit (SPU), SPI Flash controller, two channels of DMA controller, USB device, mono STN-LCD and TFT-LCD interface, interrupt controller, and many other advanced features.  Providing a complete set of common system peripherals, GPL95101UA minimizes overall system costs and eliminates many additional components that other microcontrollers may require. Its development system integrates several powerful tools such as system with C language capability, assembly compiler, linker, source debugger, and project management tools to manage a project from start to the end.

 

特性 Features

• Built-in 16-bit m’nSP® 2.0 microprocessor
• Running up to 96MHz
• Operating from 2.9V to 5.5V

• Memory
- 4K*16-bit I-cache- 10K*16-bit RAM, stack area included- Linear mapping and executing program on the external SPI FLASH.  Both 2-IO mode and 4-IO mode are supported.
• I/O
• Max. 5837 General Programmable I/O ports (GPIO).
• Each incorporates with pull-up resistor, pull-down resistor or floating input based on programmer’s settings via the corresponding registers
• 13 high driving I/O ports with LED driving capability and 40mA current sink

• Clock Management
• Internal oscillator: 8MHz ±1.5%(typ), @ 2.7V~3.6V
• 32768Hz Crystal input @ 1.62V~1.98V
• PLL (Phase-Lock Loop): 8MHz~96MHz, step=4MHz @ 2.7V~3.6V

• Flexible Power Management (Operating/ Power down/ Wait/ Halt Mode)
• Operating mode: High performance@96MHz high speed
• Deep Halt mode: 3.3V/1.8V off with only RTC on and approximately 5uA current.
• Wait mode: CPU clock off and system clocks are all on
• Halt mode: CPU and system clocks are all off. Only RTC, 32768Hz-XTAL, and LDOs modules are active

• Picture Process Unit (PPU)
• 3 Text layers + 256 Sprites
• QVGA output
• Line-base operation
• Up to 1024 x 1024 Text Size

• TFT-LCD controller
• UPS051 (serial RGB)
• UPS052 (serial RGB dummy),
• Parallel RGB
• I80 (8-bit/16-bit system bus) I/F type
• CCIR601/CCIR656.
• Supports various LCD resolutions: 160x128, 220x176, and 320x240

• Mono and 16-gray STN-LCD controller interface
• Sound Process Unit (SPU)
• 16 hardware PCM/ADPCM channels
• Cache supporting for directly accessing 16-channel wave table on external SPI Flash, 2-channel A1800 playback

• 16-channel capacitive touch detection
• Two-channel DMA controller.
• 29 interrupt sources.
• Universal Serial Bus (USB) 2.0 full speed compliant device with built-in transceiver.
• Watchdog timer.
• Independent power real-time clock.
• 11-output x 8-input matrix key scan controller.
• Eight 16-bit timers.
• Four re-loadable timers/counters support comparison, PWM, capture and BAM (4-bit angle modulation)
• SPI master/slave controller.
• Power controller with on power-on key and one system power enable output pad.
• Built-in 5.5V to 3.3V regulator, 3.3V to 1.8V regulator, Regulator for touch pad macro and regulator for ADC
• Low voltage reset(LVR)(2.4V trigger/2.6V release for 3.3V)
• IOSC, 96MHz PLL
• DAC: Two 16-bit DACs (R2R DAC for L-R speaker), 1x14-bit push-pull AMP
• ADC: Two 12-bit ADCs
• One for MIC in with PGA and digital AGC
• One for 8-channel line-in