EP1C12F256C6ES

Cyclone FPGA Family Data Sheet

Introduction TheCyclone®fieldprogrammablegatearrayfamilyisbasedona1.5-V,0.13-μm,all-layercopperSRAMprocess,withdensitiesupto20,060logicelements(LEs)andupto288KbitsofRAM.Withfeatureslikephase-lockedloops(PLLs)forclockingandadedicateddoubledatarate(DDR)

EP1C12F256C7ES

Cyclone FPGA Family Data Sheet

Introduction TheCyclone®fieldprogrammablegatearrayfamilyisbasedona1.5-V,0.13-μm,all-layercopperSRAMprocess,withdensitiesupto20,060logicelements(LEs)andupto288KbitsofRAM.Withfeatureslikephase-lockedloops(PLLs)forclockingandadedicateddoubledatarate(DDR)

EP1C12F256C8ES

Cyclone FPGA Family Data Sheet

Introduction TheCyclone®fieldprogrammablegatearrayfamilyisbasedona1.5-V,0.13-μm,all-layercopperSRAMprocess,withdensitiesupto20,060logicelements(LEs)andupto288KbitsofRAM.Withfeatureslikephase-lockedloops(PLLs)forclockingandadedicateddoubledatarate(DDR)

EP1C12F256C8N

Section I. Cyclone FPGA Family Data Sheet

Introduction TheCyclone®fieldprogrammablegatearrayfamilyisbasedona1.5-V,0.13-μm,all-layercopperSRAMprocess,withdensitiesupto20,060logicelements(LEs)andupto288KbitsofRAM.Withfeatureslikephase-lockedloops(PLLs)forclockingandadedicateddoubledatarate(DDR)

EP1C12F256I6ES

Cyclone FPGA Family Data Sheet

Introduction TheCyclone®fieldprogrammablegatearrayfamilyisbasedona1.5-V,0.13-μm,all-layercopperSRAMprocess,withdensitiesupto20,060logicelements(LEs)andupto288KbitsofRAM.Withfeatureslikephase-lockedloops(PLLs)forclockingandadedicateddoubledatarate(DDR)

EP1C12F256I7ES

Cyclone FPGA Family Data Sheet

Introduction TheCyclone®fieldprogrammablegatearrayfamilyisbasedona1.5-V,0.13-μm,all-layercopperSRAMprocess,withdensitiesupto20,060logicelements(LEs)andupto288KbitsofRAM.Withfeatureslikephase-lockedloops(PLLs)forclockingandadedicateddoubledatarate(DDR)

EP1C12F256I8ES

Cyclone FPGA Family Data Sheet

Introduction TheCyclone®fieldprogrammablegatearrayfamilyisbasedona1.5-V,0.13-μm,all-layercopperSRAMprocess,withdensitiesupto20,060logicelements(LEs)andupto288KbitsofRAM.Withfeatureslikephase-lockedloops(PLLs)forclockingandadedicateddoubledatarate(DDR)

EP1C12F256C6

Cyclone FPGA Family

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Cyclone FPGA Family

EP1C12F256C8

Cyclone FPGA Family

EP1C12F256I6

Cyclone FPGA Family

EP1C12F256I7

Cyclone FPGA Family

EP1C12F256I7N

Cyclone Device Handbook, Volume 1

EP1C12F256I8

Cyclone FPGA Family

EP1C12F256C6N

包装：托盘 封装/外壳：256-BGA 类别：集成电路（IC） FPGA（现场可编程门阵列） 描述：IC FPGA 185 I/O 256FBGA

EP1C12F256C7

包装：托盘 封装/外壳：256-BGA 类别：集成电路（IC） FPGA（现场可编程门阵列） 描述：IC FPGA 185 I/O 256FBGA

EP1C12F256C7N

包装：托盘 封装/外壳：256-BGA 类别：集成电路（IC） FPGA（现场可编程门阵列） 描述：IC FPGA 185 I/O 256FBGA