DSP56858FV120中文资料恩XP数据手册PDF规格书

DSP56858 General Description

• 120 MIPS at 120MHz

• 40K x 16-bit Program SRAM

• 24K x 16-bit Data SRAM

• 1K x 16-bit Boot ROM

• Access up to 2M words of program memory or 8M data

memory

• Chip Select Logic for glue-less interface to ROM and

SRAM

• Six (6) independent channels of DMA

• Two (2) Enhanced Synchronous Serial Interfaces (ESSI)

• Two (2) Serial Communication Interfaces (SCI)

• Serial Port Interface (SPI)

• 8-bit Parallel Host Interface

• General Purpose 16-bit Quad Timer

• JTAG/Enhanced On-Chip Emulation (OnCE™) for

unobtrusive, real-time debugging

• Computer Operating Properly (COP)/Watchdog Timer

• Time-of -Day (TOD)

• 144 LQFP and 144 MAPBGA packages

• Up to 47 GPIO

1.1 56858 Features

1.1.1 Digital Signal Processing Core

• Efficient 16-bit engine with dual Harvard architecture

• 120 Million Instructions Per Second (MIPS) at 120MHz core frequency

• Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)

• Four (4) 36-bit accumulators including extension bits

• 16-bit bidirectional shifter

• Parallel instruction set with unique DSP addressing modes

• Hardware DO and REP loops

• Three (3) internal address buses and one (1) external address bus

• Four (4) internal data buses and one (1) external data bus

• Instruction set supports both DSP and controller functions

• Four (4) hardware interrupt levels

• Five (5) software interrupt levels

• Controller-style addressing modes and instructions for compact code

• Efficient C-Compiler and local variable support

• Software subroutine and interrupt stack with depth limited only by memory

• JTAG/Enhanced OnCE debug programming interface

1.1.2 Memory

• Harvard architecture permits up to three (3) simultaneous accesses to program and data memory

• On-Chip Memory

— 40K × 16-bit Program RAM

— 24K × 16-bit Data RAM

— 1K × 16-bit Boot ROM

• Off-Chip Memory Expansion (EMI)

— Access up to 2M words of program or 8M data memory (using chip selects)

— Chip Select Logic for glue-less interface to ROM and SRAM

1.1.3 56858 Peripheral Circuit Features

• General Purpose 16-bit Quad Timer*

• Two Serial Communication Interfaces (SCI)*

• Serial Peripheral Interface (SPI) Port*

• Two (2) Enhanced Synchronous Serial Interface (ESSI) modules*

• Computer Operating Properly (COP)/Watchdog Timer

• JTAG/Enhanced On-Chip Emulation (EOnCE) for unobtrusive, real-time debugging

• Six (6) independent channels of DMA

• 8-bit Parallel Host Interface*

• Time-of-Day (TOD)

• Up to 47 GPIO

* Each peripheral I/O can be used alternately as a GPIO if not needed

1.1.4 Energy Information

• Fabricated in high-density CMOS with 3.3V, TTL-compatible digital inputs

• Wait and Stop modes available