DS90UH928QSQSLASHNOPB.A中文资料德州仪器数据手册PDF规格书

1 Features

1• Qualified for Automotive Applications AEC-Q100

– Device Temperature Grade 2: -40°C to +105°C

Ambient Operating Temperature Range

– Device HBM ESD Classification Level ±8 kV

– Device CDM ESD Classification Level C6

• Integrated HDCP Cipher Engine with On-Chip Key

Storage

• Supports HDCP Repeater Application

• Bidirectional Control Channel Interface with I2C

Compatible Serial Control Bus

• Low EMI FPD-Link Video Output

• Supports High Definition (720p) Digital Video

• RGB888 + VS, HS, DE and I2S Audio Supported

• 5 MHz to 85 MHz Pixel Clock Support

• Up to 4 I2S Digital Audio Outputs for Surround

Sound Applications

• 4 Bidirectional GPIO Channels with 2 Dedicated

Pins

• Single 3.3 V supply with 1.8 V or 3.3 V

Compatible LVCMOS I/O Interface

• AC-Coupled STP Interconnect Up to 10 Meters

• DC-Balanced and Scrambled Data with

Embedded Clock

• Adaptive Cable Equalization

• Image Enhancement (White Balance & Dithering)

and Internal Pattern Generation

• Backward Compatible Modes

2 Applications

• Automotive Displays for Navigation

• Rear Seat Entertainment Systems

3 Description

The DS90UH928Q-Q1 deserializer, in conjunction

with a DS90UH925Q-Q1 or DS90UH927Q-Q1

serializer, provides a solution for secure distribution of

content-protected digital video and audio within

automotive infotainment systems. The device

converts a high-speed serialized interface with an

embedded clock, delivered over a single signal pair

(FPD-Link III), to four LVDS data/control streams, one

LVDS clock pair (OpenLDI (FPD-Link)), and I2S

audio data. The digital video and audio data is

protected using the industry standard HDCP copy

protection scheme.The serial bus scheme, FPD-Link

III, supports high-speed forward channel data

transmission and low-speed full duplex back channel

communication over a single differential link.

Consolidation of audio, video data and control over a

single differential pair reduces the interconnect size

and weight, while also eliminating skew issues and

simplifying system design.

Adaptive input equalization of the serial input stream

provides compensation for transmission medium

losses and deterministic jitter. EMI is minimized by

the use of low voltage differential signaling.

The HDCP cipher engine is implemented in both the

serializer and deserializer. HDCP keys are stored in

on-chip memory.