DS25BR110 3.125 Gbps LVDS Buffer with Receive Equalization

1FEATURES 2• DC - 3.125 Gbps Low Jitter, High Noise Immunity, Low Power Operation • Four Levels of Receive Equalization Reduce ISI Jitter • On-Chip 100Ω Input and Output Termination Minimizes Insertion and Return Losses, Reduces Component Count, and Minimizes Board Space • 7 kV ESD on LVD

文件：542.31 Kbytes 页数：20 Pages

TI

德州仪器

DS25BR100 / DS25BR101 3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis and Receive Equalization

1FEATURES 2• DC - 3.125 Gbps Low Jitter, High Noise Immunity, Low Power Operation • Receive Equalization Reduces ISI Jitter Due to Media Loss • Transmit Pre-Emphasis Drives Lossy Backplanes and Cables • On-Chip 100Ω Input and Output Termination: – Minimizes Insertion and Return Losses – R

文件：531.49 Kbytes 页数：21 Pages

TI

德州仪器

3.125 Gbps LVDS Buffer with Receive Equalization

文件：884.02 Kbytes 页数：18 Pages

TI

德州仪器

3.125 Gbps LVDS Buffer with Receive Equalization

文件：434.57 Kbytes 页数：16 Pages

NSCNational Semiconductor (TI)

美国国家半导体美国国家半导体公司

具有接收均衡功能的 3.125Gbps LVDS 缓冲器

The DS25BR110 is a single channel 3.125 Gbps LVDS buffer optimized for high-speed signal transmission over lossy FR-4 printed circuit board backplanes and balanced metallic cables. A fully differential signal path ensures exceptional signal integrity and noise immunity.The DS25BR110 features four le • DC - 3.125 Gbps Low Jitter, High Noise Immunity, Low Power Operation\n• Four Levels of Receive Equalization Reduce ISI Jitter\n• On-Chip 100Ω Input and Output Termination Minimizes Insertion and Return Losses, Reduces Component Count, and Minimizes Board Space\n• 7 kV ESD on LVDS I/O Pins Protects;

TI

德州仪器

丝印：2R110；Package：WSON；DS25BR110 3.125 Gbps LVDS Buffer with Receive Equalization

1FEATURES 2• DC - 3.125 Gbps Low Jitter, High Noise Immunity, Low Power Operation • Four Levels of Receive Equalization Reduce ISI Jitter • On-Chip 100Ω Input and Output Termination Minimizes Insertion and Return Losses, Reduces Component Count, and Minimizes Board Space • 7 kV ESD on LVD

文件：542.31 Kbytes 页数：20 Pages

TI

德州仪器

丝印：2R110；Package：WSON；DS25BR110 3.125 Gbps LVDS Buffer with Receive Equalization

1FEATURES 2• DC - 3.125 Gbps Low Jitter, High Noise Immunity, Low Power Operation • Four Levels of Receive Equalization Reduce ISI Jitter • On-Chip 100Ω Input and Output Termination Minimizes Insertion and Return Losses, Reduces Component Count, and Minimizes Board Space • 7 kV ESD on LVD

文件：542.31 Kbytes 页数：20 Pages

TI

德州仪器

丝印：2R110；Package：WSON；DS25BR110 3.125 Gbps LVDS Buffer with Receive Equalization

1FEATURES 2• DC - 3.125 Gbps Low Jitter, High Noise Immunity, Low Power Operation • Four Levels of Receive Equalization Reduce ISI Jitter • On-Chip 100Ω Input and Output Termination Minimizes Insertion and Return Losses, Reduces Component Count, and Minimizes Board Space • 7 kV ESD on LVD

文件：542.31 Kbytes 页数：20 Pages

TI

德州仪器

丝印：2R110；Package：WSON；DS25BR110 3.125 Gbps LVDS Buffer with Receive Equalization

1FEATURES 2• DC - 3.125 Gbps Low Jitter, High Noise Immunity, Low Power Operation • Four Levels of Receive Equalization Reduce ISI Jitter • On-Chip 100Ω Input and Output Termination Minimizes Insertion and Return Losses, Reduces Component Count, and Minimizes Board Space • 7 kV ESD on LVD

文件：542.31 Kbytes 页数：20 Pages

TI

德州仪器

丝印：2R110；Package：WSON；DS25BR110 3.125 Gbps LVDS Buffer with Receive Equalization

1FEATURES 2• DC - 3.125 Gbps Low Jitter, High Noise Immunity, Low Power Operation • Four Levels of Receive Equalization Reduce ISI Jitter • On-Chip 100Ω Input and Output Termination Minimizes Insertion and Return Losses, Reduces Component Count, and Minimizes Board Space • 7 kV ESD on LVD

文件：542.31 Kbytes 页数：20 Pages

TI

德州仪器