DS25BR110

DS25BR110 3.125 Gbps LVDS Buffer with Receive Equalization

1FEATURES 2•DC-3.125GbpsLowJitter,HighNoise Immunity,LowPowerOperation •FourLevelsofReceiveEqualizationReduce ISIJitter •On-Chip100ΩInputandOutputTermination MinimizesInsertionandReturnLosses, ReducesComponentCount,andMinimizes BoardSpace •7kVESDonLVD

DS25BR110

DS25BR100 / DS25BR101 3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis and Receive Equalization

1FEATURES 2•DC-3.125GbpsLowJitter,HighNoise Immunity,LowPowerOperation •ReceiveEqualizationReducesISIJitterDueto MediaLoss •TransmitPre-EmphasisDrivesLossy BackplanesandCables •On-Chip100ΩInputandOutputTermination: –MinimizesInsertionandReturnLosses –R

DS25BR110

具有接收均衡功能的 3.125Gbps LVDS 缓冲器; • DC - 3.125 Gbps Low Jitter, High Noise Immunity, Low Power Operation\n• Four Levels of Receive Equalization Reduce ISI Jitter\n• On-Chip 100Ω Input and Output Termination Minimizes Insertion and Return Losses, Reduces Component Count, and Minimizes Board Space\n• 7 kV ESD on LVDS I/O Pins Protects Adjoining Components\n• Small 3 mm x 3 mm 8-WSON Space Saving Package;

The DS25BR110 is a single channel 3.125 Gbps LVDS buffer optimized for high-speed signal transmission over lossy FR-4 printed circuit board backplanes and balanced metallic cables. A fully differential signal path ensures exceptional signal integrity and noise immunity.The DS25BR110 features four levels of receive equalization (EQ), making it ideal for use as a receiver device. Other LVDS devices with similar IO characteristics include the following products. The DS25BR120 features four levels of pre-emphasis for use as an optimized driver device, while the DS25BR100 features both pre-emphasis and equalization for use as an optimized repeater device. The DS25BR150 is a buffer/repeater with the lowest power consumption and does not feature transmit pre-emphasis nor receive equalization.Wide input common mode range allows the receiver to accept signals with LVDS, CML and LVPECL levels; the output levels are LVDS. A very small package footprint requires minimal space on the board while the flow-through pinout allows easy board layout. The differential inputs and outputs are internally terminated with a 100Ω resistor to lower device input and output return losses, reduce component count, and further minimize board space.

DS25BR110

3.125 Gbps LVDS Buffer with Receive Equalization

DS25BR110

3.125 Gbps LVDS Buffer with Receive Equalization

DS25BR110TSD/NOPB

丝印：2R110；Package：WSON；DS25BR110 3.125 Gbps LVDS Buffer with Receive Equalization

1FEATURES 2•DC-3.125GbpsLowJitter,HighNoise Immunity,LowPowerOperation •FourLevelsofReceiveEqualizationReduce ISIJitter •On-Chip100ΩInputandOutputTermination MinimizesInsertionandReturnLosses, ReducesComponentCount,andMinimizes BoardSpace •7kVESDonLVD

DS25BR110TSD/NOPB.A

丝印：2R110；Package：WSON；DS25BR110 3.125 Gbps LVDS Buffer with Receive Equalization

1FEATURES 2•DC-3.125GbpsLowJitter,HighNoise Immunity,LowPowerOperation •FourLevelsofReceiveEqualizationReduce ISIJitter •On-Chip100ΩInputandOutputTermination MinimizesInsertionandReturnLosses, ReducesComponentCount,andMinimizes BoardSpace •7kVESDonLVD

DS25BR110TSDSLASHNOPB

丝印：2R110；Package：WSON；DS25BR110 3.125 Gbps LVDS Buffer with Receive Equalization

1FEATURES 2•DC-3.125GbpsLowJitter,HighNoise Immunity,LowPowerOperation •FourLevelsofReceiveEqualizationReduce ISIJitter •On-Chip100ΩInputandOutputTermination MinimizesInsertionandReturnLosses, ReducesComponentCount,andMinimizes BoardSpace •7kVESDonLVD

DS25BR110TSDSLASHNOPB.A

丝印：2R110；Package：WSON；DS25BR110 3.125 Gbps LVDS Buffer with Receive Equalization

1FEATURES 2•DC-3.125GbpsLowJitter,HighNoise Immunity,LowPowerOperation •FourLevelsofReceiveEqualizationReduce ISIJitter •On-Chip100ΩInputandOutputTermination MinimizesInsertionandReturnLosses, ReducesComponentCount,andMinimizes BoardSpace •7kVESDonLVD

DS25BR110TSDX/NOPB

丝印：2R110；Package：WSON；DS25BR110 3.125 Gbps LVDS Buffer with Receive Equalization

1FEATURES 2•DC-3.125GbpsLowJitter,HighNoise Immunity,LowPowerOperation •FourLevelsofReceiveEqualizationReduce ISIJitter •On-Chip100ΩInputandOutputTermination MinimizesInsertionandReturnLosses, ReducesComponentCount,andMinimizes BoardSpace •7kVESDonLVD