DS218

DiskStation DS218

Highlights •Versatile2-bayNASforsmalloffices andhomeusers •64-bitquad-coreprocessordelivering sequentialthroughputatover112 MB/sreadingand112MB/swriting1 •2GBDDR4memory,4timesthe capacitythanitspredecessor •4K10-bitH.265videotranscodingon thefly2 •R

DS2180A

T1 Transceiver

DESCRIPTION TheDS2180AisamonolithicCMOSdevicedesignedtoimplementprimaryrate(1.544MHz)T-carriertransmissionsystems.The193SframingmodeisintendedtosupportexistingFt/Fsapplications(12frames/superframe).The193Eframingmodesupportstheextendedsuperframeformat(24fra

DS2180A

T1收发器; \n• Single-chip DS1 rate transceiver \n• Supports common framing standards\n• 12 frames/superframe \"193S\" \n• 24 frames/superframe \"193E\"\n• Three zero suppression modes:\n• B7 stuffing \n• B8ZS \n• Transparent\n• Simple serial interface used for configuration, control and status monitoring in processor mode \n• Hardware mode requires no host processor; intended for standalone applications \n• Selectable 0, 2, 4, 16-state robbed-bit signaling modes \n• Allows mix of clear and non-clear DS0 channels on same DS1 link \n• Alarm generation and detection \n• Receive error detection and counting for transmission performance monitoring \n• 5V supply, low-power CMOS technology \n• Surface-mount package available, designated DS2180AQ \n• Industrial temperature range of -40°C to +85°C available, designated DS2180AN or DS2180AQN \n• Compatible to DS2186 transmit line interface, DS2187 receive line interface, DS2188 jitter attenuator, DS2175 T1/CEPT elastic store, DS2290 T1 isolation stik, and DS2291 T1 long loop stik;

The DS2180A is a monolithic CMOS device designed to implement primary rate (1.544MHz) T-carrier transmission systems. The 193S framing mode is intended to support existing Ft/Fs applications (12 frames/superframe). The 193E framing mode supports the extended superframe format (24 frames/superframe). Clear-channel capability is provided by selection of appropriate zero suppression and signaling modes.\n Several functional blocks exist in the transceiver. The transmit framer/formatter generates appropriate framing bits, inserts robbed bit signaling, supervises zero suppression, generates alarms, and provides output clocks useful for data conditioning and decoding. The receive synchronizer establishes frame and multiframe boundaries by identifying frame signaling bits, extracts signaling data, reports alarms and transmission errors, and provides output clocks useful for data conditioning and decoding.\n The control block is shared between transmit and receive sides. This block determines the frame, zero suppression, alarm and signaling formats. User access to the control block is by one of two modes. In the processor mode, pins 14 through 18 are a microprocessor/microcontroller-compatible serial port that can be used for device configuration, control, and status monitoring.\n In the hardware mode, no off-board processor is required. Pins 14 through 18 are reconfigured into hardwired select pins. Features such as selection clear DS0 channels, insertion of idle code and alteration of sync algorithm are unavailable in the hardware mode.

DS2181A

CEPT一次群速率收发器; \n• Single-chip primary-rate transceiver meets CCITT standards G.704, G.706 and G.732 \n• Supports new CRC4-based framing standards and CAS and CCS signaling standards \n• Simple serial interface used for device configuration and control in processor mode \n• Hardware mode requires no host processor; intended for standalone applications \n• Comprehensive on-chip alarm generation, alarm detection, and error logging logic \n• Shares footprint with DS2180A T1 transceiver \n• Comparison to DS2175 T1/CEPT elastic store, DS2186 transmit line interface, DS2187 receive line interface, and DS2188 jitter attenuator \n• 5V supply; low-power CMOS technology;

The DS2181A is designed for use in CEPT networks and supports all logical requirements of CCITT Red Book recommendations G.704, G.706, and G.732. The transmit side generates framing patterns and CRC4 codes, formats outgoing channel and signaling data, and produces network alarm codes when enabled. The receive side decodes the incoming data and establishes frame, CAS multiframe, and CRC4 multiframe alignments. Once synchronized, the device extracts channel, signaling, and alarm data.\n A serial port allows access to 14 on-chip control and status registers in the processor mode. In this mode, a host processor controls features such as error logging, per-channel code manipulation, and alteration of the receive synchronizer algorithm.\n The hardware mode is intended for preliminary system prototyping and/or retrofitting into existing systems. This mode requires no host processor and disables special features available in the processor mode.

DS2181A

CEPT Primary Rate Transceiver

DESCRIPTION TheDS2181AisdesignedforuseinCEPTnetworksandsupportsalllogicalrequirementsofCCITTRedBookRecommendationsG.704,G.706andG.732.ThetransmitsidegeneratesframingpatternsandCRC4codes,formatsoutgoingchannelandsignalingdata,andproducesnetworkalarmcodesw

DS2182

T1 Line Monitor

DESCRIPTION TheDS2182AT1linemonitorchipisamonolithicCMOSdevicedesignedtomonitorreal-timeperformanceonT1lines.TheDS2182Aframestothedataontheline,countserrors,andsuppliesdetailedinformationaboutthestatusandconditionoftheline.Largeon-boardcountersallowth

DS2182A

T1 Line Monitor

DESCRIPTION TheDS2182AT1linemonitorchipisamonolithicCMOSdevicedesignedtomonitorreal-timeperformanceonT1lines.TheDS2182Aframestothedataontheline,countserrors,andsuppliesdetailedinformationaboutthestatusandconditionoftheline.Largeon-boardcountersallowth

DS2186

Transmit Line Interface

DESCRIPTION TheDS2186T1/CEPTTransmitLineInterfaceChipinterfacesuserequipmenttoNorthAmerican(T1–1.544MHz)andEuropean(CEPT–2.048MHz)primaryratecommunicationsnetworks.Thedeviceiscompatiblewithalltypesoftwistedpairandcoaxcablefoundinsuchnetworks. FEATURES •Li

DS2187

Receive Line Interface

DESCRIPTION TheDS2187T1/CEPTReceiveLineInterfacechipinterfacesuserequipmenttoNorthAmerican(T11.544MHz)andEuropean(CEPT2.048MHz)primaryratecommunicationnetworks.Thedeviceextractsclockanddatafromtwistedpairorcoaxtransmissionmediaandeliminatesexpensivediscret

DS2188

T1/CEPT Jitter Attenuator

DESCRIPTION TheDS2188T1/CEPTJitterAttenuatorChipcontainsa128X2-bitbufferwhich,inconjunctionwithanexternal4Xcrystal,isusedtoattenuatetheincomingjitterpresentinclockanddata.ThedevicemeetsallofthelatestapplicablespecificationsincludingthoseoutlinedinTR62