DM74LS533N中文资料仙童半导体数据手册PDF规格书

General Description

The DM74LS533 consists of eight latches with 3-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup times is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH the bus output is in the high impedance state. The DM74LS533 is the same as the DM74LS373, except that the outputs are inverted. For detailed specifications please see the DM74LS373 data sheet, but note that the propagation delays from data to output are 5.0 ns longer for the DM74LS533 than for the DM74LS373.

Features

■ Eight latches in a single package

■ 3-STATE outputs for bus interfacing