CDCU877ARHARG4集成电路（IC）的应用特定时钟/定时规格书PDF中文资料

CDCU877ARHARG4属于集成电路（IC）的应用特定时钟/定时。由德州仪器制造生产的CDCU877ARHARG4应用特定时钟/定时专用时钟和计时 IC（集成电路）产品族中的产品主要用于执行与时间或频率信息生成和分配相关的各种操作，适合的设计环境较特定，例如 AMD 和 Intel 的中央处理单元 (CPU) 或图形处理单元 (GPU)、DVD 音频设备、蓝光光盘播放器、以太网设备、PCIe、SATA、光纤通道接口、车载娱乐总线等。

FEATURES

· 1.8-V Phase Lock Loop Clock Driver for

Double Data Rate (DDR II) Applications

· Spread Spectrum Clock Compatible

· Operating Frequency: 10 MHz to 400 MHz

· Low Current Consumption: <135 mA

· Low Jitter (Cycle-Cycle): ±30 ps

· Low Output Skew: 35 ps

· Low Period Jitter: ±20 ps

· Low Dynamic Phase Offset: ±15 ps

· Low Static Phase Offset: ±50 ps

· Distributes One Differential Clock Input to Ten

Differential Outputs

· 52-Ball μBGA (MicroStar™ Junior BGA,

0,65-mm pitch) and 40-Pin MLF

· External Feedback Pins (FBIN, FBIN) are Used

to Synchronize the Outputs to the Input

Clocks

· Meets or Exceeds JESD82-8 PLL Standard for

PC2-3200/4300

· Fail-Safe Inputs

DESCRIPTION

The CDCU877 is a high-performance, low-jitter, low-skew, zero-delay buffer that distributes a differential clock

input pair (CK, CK) to ten differential pairs of clock outputs (Yn, Yn) and to one differential pair of feedback clock

outputs (FBOUT, FBOUT). The clock outputs are controlled by the input clocks (CK, CK), the feedback clocks

(FBIN, FBIN), the LVCMOS control pins (OE, OS), and the analog power input (AVDD). When OE is low, the

clock outputs, except FBOUT/FBOUT, are disabled while the internal PLL continues to maintain its locked-in

frequency. OS (output select) is a program pin that must be tied to GND or VDD. When OS is high, OE functions

as previously described. When OS and OE are both low, OE has no affect on Y7/Y7, they are free running.

When AVDD is grounded, the PLL is turned off and bypassed for test purposes.

When both clock inputs (CK, CK) are logic low, the device enters in a low power mode. An input logic detection

circuit on the differential inputs, independent from input buffers, detects the logic low level and performs in a low

power state where all outputs, the feedback, and the PLL are off. When the clock inputs transition from being

logic low to being differential signals, the PLL turns back on, the inputs and the outputs are enabled, and the

PLL obtains phase lock between the feedback clock pair (FBIN, FBIN) and the clock input pair (CK, CK) within

the specified stabilization time.

The CDCU877 is able to track spread spectrum clocking (SSC) for reduced EMI. This device operates from

—40°C to 85°C.