Dual 1:8 Low Additive Jitter LVDS Buffer

1FEATURES • Dual 1:8 Differential Buffer • Low Additive Jitter

文件：1.22653 Mbytes 页数：19 Pages

TI

德州仪器

Dual 1:8 Low Additive Jitter LVDS Buffer

文件：778.56 Kbytes 页数：20 Pages

TI

德州仪器

丝印：CDCLVD2108；Package：VQFN；Dual 1:8 Low Additive Jitter LVDS Buffer

1FEATURES • Dual 1:8 Differential Buffer • Low Additive Jitter

文件：1.22653 Mbytes 页数：19 Pages

TI

德州仪器

丝印：CDCLVD2108；Package：VQFN；Dual 1:8 Low Additive Jitter LVDS Buffer

1FEATURES • Dual 1:8 Differential Buffer • Low Additive Jitter

文件：1.22653 Mbytes 页数：19 Pages

TI

德州仪器

丝印：CDCLVD2108；Package：VQFN；Dual 1:8 Low Additive Jitter LVDS Buffer

1FEATURES • Dual 1:8 Differential Buffer • Low Additive Jitter

文件：1.22653 Mbytes 页数：19 Pages

TI

德州仪器

丝印：CDCLVD2108；Package：VQFN；Dual 1:8 Low Additive Jitter LVDS Buffer

1FEATURES • Dual 1:8 Differential Buffer • Low Additive Jitter

文件：1.22653 Mbytes 页数：19 Pages

TI

德州仪器

丝印：CDCLVD2108；Package：VQFN；Dual 1:8 Low Additive Jitter LVDS Buffer

1FEATURES • Dual 1:8 Differential Buffer • Low Additive Jitter

文件：1.22653 Mbytes 页数：19 Pages

TI

德州仪器

低抖动双路 1:8 通用至 LVDS 缓冲器

The CDCLVD2108 clock buffer distributes two clock inputs (IN0, IN1) to a total of 16 pairs of differential LVDS clock outputs (OUT0, OUT15). Each buffer block consists of one input and 8 LVDS outputs. The inputs can either be LVDS, LVPECL, or LVCMOS. The CDCLVD2108 is specifically designed for drivi • Dual 1:8 Differential Buffer\n• Low Additive Jitter 10 kHz to 20 MHz\n• Low Within Bank Output Skew of 50 ps (Max)\n• Universal Inputs Accept LVDS, LVPECL, LVCMOS\n• One Input Dedicated for Eight Outputs\n• Total of 16 LVDS Outputs, ANSI EIA/TIA-644A Standard Compatible\n• Clock Frequency up to 80;

TI

德州仪器

Dual 1:8 Low Additive Jitter LVDS Buffer

文件：778.56 Kbytes 页数：20 Pages

TI

德州仪器

Dual 1:8 Low Additive Jitter LVDS Buffer

文件：778.56 Kbytes 页数：20 Pages

TI

德州仪器