CD74HCT7046AM96集成电路（IC）的时钟发生器PLL频率合成器规格书PDF中文资料

CD74HCT7046AM96属于集成电路（IC）的时钟发生器PLL频率合成器。由美国德州仪器公司制造生产的CD74HCT7046AM96时钟发生器，PLL，频率合成器时钟发生器、PLL 和频率合成器集成电路 (IC) 可为逻辑器件提供参考信号的稳定定时脉冲，这些器件包括计算机、微控制器、数据通信系统和图形/视频发生器。这些集成电路可能包括缓冲器、驱动器、分频器、倍频器、多路复用器、合成器、扇出分配器和预分频器。

Features

• Center Frequency of 18MHz (Typ) at VCC = 5V,

Minimum Center Frequency of 12MHz at VCC = 4.5V

• Choice of Two Phase Comparators

- Exclusive-OR

- Edge-Triggered JK Flip-Flop

• Excellent VCO Frequency Linearity

• VCO-Inhibit Control for ON/OFF Keying and for Low

Standby Power Consumption

• Minimal Frequency Drift

• Zero Voltage Offset Due to Op-Amp Buffer

• Operating Power-Supply Voltage Range

- VCO Section . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 6V

- Digital Section . . . . . . . . . . . . . . . . . . . . . . . . 2V to 6V

• Fanout (Over Temperature Range)

- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55oC to 125oC

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: NIL = 30%, NIH = 30% of VCC

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

VIL= 0.8V (Max), VIH = 2V (Min)

- CMOS Input Compatibility, Il ≤ 1μA at VOL, VOH

Applications

• FM Modulation and Demodulation

• Frequency Synthesis and Multiplication

• Frequency Discrimination

• Tone Decoding

• Data Synchronization and Conditioning

• Voltage-to-Frequency Conversion

• Motor-Speed Control

• Related Literature

- AN8823, CMOS Phase-Locked-Loop Application

Using the CD74HC/HCT7046A and

CD74HC/HCT7046A

Description

The CD74HC7046A and CD74HCT7046A high-speed

silicon-gate CMOS devices, specified in compliance with

JEDEC Standard No. 7A, are phase-locked-loop (PLL)

circuits that contain a linear voltage-controlled oscillator

(VCO), two-phase comparators (PC1, PC2), and a lock

detector. A signal input and a comparator input are common

to each comparator. The lock detector gives a HIGH level at

pin 1 (LD) when the PLL is locked. The lock detector

capacitor must be connected between pin 15 (CLD) and pin

8 (Gnd). For a frequency range of 100kHz to 10MHz, the

lock detector capacitor should be 1000pF to 10pF,

respectively.

The signal input can be directly coupled to large voltage

signals, or indirectly coupled (with a series capacitor) to

small voltage signals. A self-bias input circuit keeps small

voltage signals within the linear region of the input amplifiers.

With a passive low-pass filter, the 7046A forms a secondorder

loop PLL. The excellent VCO linearity is achieved by

the use of linear op-amp techniques.