CD74HCT4024

高速 CMOS 逻辑 7 级二进制纹波计数器; • Fully Static Operation\n• Buffered Inputs\n• Common Reset\n• Negative Edge Clocking\n• Fanout (Over Temperature Range) \n• Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads\n• Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads\n \n• Wide Operating Temperature Range . . . -55°C to 125°C\n• Balanced Propagation Delay and Transition Times\n• Significant Power Reduction Compared to LSTTL Logic ICs\n• HC Types \n• 2V to 6V Operation\n• High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V\n \n• HCT Types \n• 4.5V to 5.5V Operation\n• Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)\n• CMOS Input Compatibility, Il 1µA at VOL, VOH;

The ’HC4024 and ’HCT4024 are 7-stage ripple-carry binary counters. All counter stages are master-slave flip-flops. The state of the stage advances one count on the negative transition of each input pulse; a high voltage level on the MR line resets all counters to their zero state. All inputs and outputs are buffered.

CD74HCT4024

High Speed CMOS Logic 7-Stage Binary Ripple Counter

CD74HCT4024

High-Speed CMOS Logic 7-Stage Binary Ripple Counter

CD74HCT4024

High-Speed CMOS Logic 7-Stage Binary Ripple Counter

CD74HCT4024

High-Speed CMOS Logic 7-Stage Binary Ripple Counter

CD74HCT4024

High-Speed CMOS Logic 7-Stage Binary Ripple Counter

CD74HCT4024E

High-Speed CMOS Logic 7-Stage Binary Ripple Counter

CD74HCT4024E

High-Speed CMOS Logic 7-Stage Binary Ripple Counter

CD74HCT4024E

High-Speed CMOS Logic 7-Stage Binary Ripple Counter

CD74HCT4024E

High-Speed CMOS Logic 7-Stage Binary Ripple Counter