CDx4HC11 Triple 3-Input AND Gates

1 Features • Buffered inputs • Wide operating voltage range: 2 V to 6 V • Wide operating temperature range: –55°C to +125°C • Supports fanout up to 10 LSTTL loads • Significant power reduction compared to LSTTL logic ICs 2 Applications • Combining power good signals • Enable digital si

文件：1.20587 Mbytes 页数：26 Pages

TI

德州仪器

High Speed CMOS Logic Triple 3-Input AND Gate

文件：33.84 Kbytes 页数：6 Pages

TI

德州仪器

High-Speed CMOS Logic Triple 3-Input AND Gate

文件：260.86 Kbytes 页数：11 Pages

TI

德州仪器

丝印：CD74HC112E；Package：PDIP；CDx4HC112, CDx4HCT112 Dual J-K Flip-Flop with Set and Reset with Negative-Edge Trigger

1 Features • Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times • Asynchronous set and reset • Complementary outputs • Buffered inputs • Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25℃ • Fanout (over temperature range) – Standard output

文件：1.3793 Mbytes 页数：29 Pages

TI

德州仪器

丝印：CD74HC11E；Package：PDIP；CDx4HC11 Triple 3-Input AND Gates

1 Features • Buffered inputs • Wide operating voltage range: 2 V to 6 V • Wide operating temperature range: –55°C to +125°C • Supports fanout up to 10 LSTTL loads • Significant power reduction compared to LSTTL logic ICs 2 Applications • Combining power good signals • Enable digital si

文件：1.20587 Mbytes 页数：26 Pages

TI

德州仪器

丝印：CD74HC11E；Package：PDIP；CDx4HC11 Triple 3-Input AND Gates

1 Features • Buffered inputs • Wide operating voltage range: 2 V to 6 V • Wide operating temperature range: –55°C to +125°C • Supports fanout up to 10 LSTTL loads • Significant power reduction compared to LSTTL logic ICs 2 Applications • Combining power good signals • Enable digital si

文件：1.20587 Mbytes 页数：26 Pages

TI

德州仪器

3 通道、3 输入、2V 至 6V 与门

This device contains three independent 3-input AND gates. Each gate performs the Boolean function Y = A ● B ● C in positive logic. • Buffered inputs\n• Wide operating voltage range: 2 V to 6 V\n• Wide operating temperature range: –55°C to +125°C\n• Supports fanout up to 10 LSTTL loads\n• Significant power reduction compared to LSTTL logic ICs;

TI

德州仪器

CDx4HC112, CDx4HCT112 Dual J-K Flip-Flop with Set and Reset with Negative-Edge Trigger

1 Features • Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times • Asynchronous set and reset • Complementary outputs • Buffered inputs • Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25℃ • Fanout (over temperature range) – Standard output

文件：1.3793 Mbytes 页数：29 Pages

TI

德州仪器

丝印：HC112M；Package：SOIC；CDx4HC112, CDx4HCT112 Dual J-K Flip-Flop with Set and Reset with Negative-Edge Trigger

1 Features • Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times • Asynchronous set and reset • Complementary outputs • Buffered inputs • Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25℃ • Fanout (over temperature range) – Standard output

文件：1.3793 Mbytes 页数：29 Pages

TI

德州仪器

丝印：HC112M；Package：SOIC；CDx4HC112, CDx4HCT112 Dual J-K Flip-Flop with Set and Reset with Negative-Edge Trigger

1 Features • Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times • Asynchronous set and reset • Complementary outputs • Buffered inputs • Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25℃ • Fanout (over temperature range) – Standard output

文件：1.3793 Mbytes 页数：29 Pages

TI

德州仪器