Dual J-K Flip-Flop with Reset Negative-Edge Trigger

Features • Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times • Asynchronous Reset • Complementary Outputs • Buffered Inputs • Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25oC • Fanout (Over Temperature Range) - Standard Outputs . . . . .

文件：609.54 Kbytes 页数：20 Pages

TI

德州仪器

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

文件：56.86 Kbytes 页数：8 Pages

TI

德州仪器

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

文件：451.69 Kbytes 页数：15 Pages

TI

德州仪器

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

文件：624.14 Kbytes 页数：16 Pages

TI

德州仪器

丝印：CD74HC107E；Package：PDIP；Dual J-K Flip-Flop with Reset Negative-Edge Trigger

Features • Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times • Asynchronous Reset • Complementary Outputs • Buffered Inputs • Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25oC • Fanout (Over Temperature Range) - Standard Outputs . . . . .

文件：609.54 Kbytes 页数：20 Pages

TI

德州仪器

丝印：CD74HC107E；Package：PDIP；Dual J-K Flip-Flop with Reset Negative-Edge Trigger

Features • Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times • Asynchronous Reset • Complementary Outputs • Buffered Inputs • Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25oC • Fanout (Over Temperature Range) - Standard Outputs . . . . .

文件：609.54 Kbytes 页数：20 Pages

TI

德州仪器

丝印：CD74HC107E；Package：PDIP；Dual J-K Flip-Flop with Reset Negative-Edge Trigger

Features • Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times • Asynchronous Reset • Complementary Outputs • Buffered Inputs • Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25oC • Fanout (Over Temperature Range) - Standard Outputs . . . . .

文件：609.54 Kbytes 页数：20 Pages

TI

德州仪器

具有复位功能的高速 CMOS 逻辑双路负边沿触发式 J-K 触发器

The ’HC107 and ’HCT107 utilize silicon gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. They exhibit the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads.\n\n These flip-flops have independent J, K, Reset and Clo • Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times\n• Complementary Outputs\n• Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25°C\n• Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads\n• Wide Operating Temperature Range . . . -55°C to 125°;

TI

德州仪器

丝印：HC107M；Package：SOIC；Dual J-K Flip-Flop with Reset Negative-Edge Trigger

Features • Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times • Asynchronous Reset • Complementary Outputs • Buffered Inputs • Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25oC • Fanout (Over Temperature Range) - Standard Outputs . . . . .

文件：609.54 Kbytes 页数：20 Pages

TI

德州仪器

丝印：HC107M；Package：SOIC；Dual J-K Flip-Flop with Reset Negative-Edge Trigger

Features • Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times • Asynchronous Reset • Complementary Outputs • Buffered Inputs • Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25oC • Fanout (Over Temperature Range) - Standard Outputs . . . . .

文件：609.54 Kbytes 页数：20 Pages

TI

德州仪器