DECADE COUNTER/DIVIDER WITH TEN DECODED OUTPUTS

2-V to 6-V Operation Fully Static Operation Buffered Inputs Common Reset Positive-Edge Clocking Balanced Propagation Delay and Transition Times High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5 V Packaged in Ceramic (F) DIP Package and Also Available in Chip Form (H)

文件：275.83 Kbytes 页数：12 Pages

TI

德州仪器

HIGH-SPEED CMOS LOGIC DECADE COUNTER/DIVIDER WITH 10 DECODED OUTPUTS

Controlled Baseline − One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of −40°C to 125°C Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product-Change Notification Qualification Pedigree† Fully Static Operation Buffered Inputs Common Reset

文件：422.7 Kbytes 页数：16 Pages

TI

德州仪器

HIGH-SPEED CMOS LOGIC DECADE COUNTER/DIVIDER WITH 10 DECODED OUTPUTS

Qualified for Automotive Applications Fully Static Operation Buffered Inputs Common Reset Positive Edge Clocking Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25°C Fanout (Over Temperature Range) − Standard Outputs . . . 10 LSTTL Loads − Bus Driver Outputs . . . 15 LSTTL Loads Bal

文件：384.95 Kbytes 页数：15 Pages

TI

德州仪器

High-Speed CMOS Logic Decade Counter/Divider with 10 Decoded Outputs

Features • Fully Static Operation • Buffered Inputs • Common Reset • Positive Edge Clocking • Typical fMAX = 50MHz at VCC = 5V, CL = 15pF, TA = 25oC • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . .

文件：738.58 Kbytes 页数：22 Pages

TI

德州仪器

High-Speed CMOS Logic Decade Counter/Divider with 10 Decoded Outputs

文件：347.51 Kbytes 页数：14 Pages

TI

德州仪器

High-Speed CMOS Logic Decade Counter/Divider with 10 Decoded Outputs

文件：497.87 Kbytes 页数：16 Pages

TI

德州仪器

High-Speed CMOS Logic Decade Counter/Divider with 10 Decoded Outputs

文件：528.36 Kbytes 页数：16 Pages

TI

德州仪器

具有 10 个解码输出的高速 CMOS 逻辑十进制计数器/除法器

The CD54HC4017 is a high-speed silicon-gate CMOS 5-stage Johnson counter with ten decoded outputs. Each decoded output normally is low and sequentially goes high on the low-to-high transition of the clock (CP) input. Each output stays high for one clock period of the ten-clock-period cycle. The term • 2-V to 6-V Operation• Fully Static Operation• Buffered Inputs• Common Reset• Positive-Edge Clocking• Balanced Propagation Delay and Transition Times• High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5 V• Packaged in Ceramic (F) DIP Package and Also Available in Chip Form (H);

TI

德州仪器

丝印：8601101EA；Package：CDIP；DECADE COUNTER/DIVIDER WITH TEN DECODED OUTPUTS

2-V to 6-V Operation Fully Static Operation Buffered Inputs Common Reset Positive-Edge Clocking Balanced Propagation Delay and Transition Times High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5 V Packaged in Ceramic (F) DIP Package and Also Available in Chip Form (H)

文件：275.83 Kbytes 页数：12 Pages

TI

德州仪器

丝印：8601101EA；Package：CDIP；High-Speed CMOS Logic Decade Counter/Divider with 10 Decoded Outputs

Features • Fully Static Operation • Buffered Inputs • Common Reset • Positive Edge Clocking • Typical fMAX = 50MHz at VCC = 5V, CL = 15pF, TA = 25oC • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . .

文件：738.58 Kbytes 页数：22 Pages

TI

德州仪器