14-bit bus switch/multiplexer for DDR2/DDR3/DDR4 applications

文件：109.48 Kbytes 页数：13 Pages

PHI

飞利浦

14-bit bus switch/multiplexer for DDR2-DDR3 applications

文件：102.5 Kbytes 页数：14 Pages

恩XP

14-bit bus switch/multiplexer for DDR2-DDR3 applications

文件：102.5 Kbytes 页数：14 Pages

恩XP

14-bit bus switch/multiplexer for DDR2/DDR3/DDR4 applications

文件：109.48 Kbytes 页数：13 Pages

PHI

飞利浦

14-bit bus switch/multiplexer for DDR2/DDR3/DDR4 applications

文件：109.48 Kbytes 页数：13 Pages

PHI

飞利浦

14-bit bus switch/multiplexer for DDR2/DDR3/DDR4 applications

This 14-bit bus switch/multiplexer (MUX) is designed for 1.5 V or 1.8 V supply voltageoperation, POD_12, SSTL_12, SSTL_135, SSTL_15 or SSTL_18 signaling and CMOSselect input levels. It is designed for operation in DDR2, DDR3 or DDR4 memory bussystems.\nThe CBTW28DD14 has a 1 : 2 switch or 2 : 1 mult Topology14-bit bus width\n1 : 2 switch/MUX topology\nBidirectional operation\nSimple CMOS select pin (SEL)\nSimple CMOS enable pin (EN)\nPerformance2.5 GHz bandwidth\nLow ON insertion loss\nLow crosstalk\nHigh OFF isolation\nPOD_12, SSTL_12, SSTL_135, SSTL_15 or SSTL_18 signaling\nLow RON (10 Ω typi;

恩XP

恩智浦

14-bit bus switch/multiplexer for DDR2/DDR3/DDR4 applications

This 14-bit bus switch/multiplexer (MUX) is designed for 1.5 V or 1.8 V supply voltageoperation, POD_12, SSTL_12, SSTL_135, SSTL_15 or SSTL_18 signaling and CMOSselect input levels. It is designed for operation in DDR2, DDR3 or DDR4 memory bussystems.\nThe CBTW28DD14 has a 1 : 2 switch or 2 : 1 mult Topology14-bit bus width\n1 : 2 switch/MUX topology\nBidirectional operation\nSimple CMOS select pin (SEL)\nSimple CMOS enable pin (EN)\nPerformance2.5 GHz bandwidth\nLow ON insertion loss\nLow crosstalk\nHigh OFF isolation\nPOD_12, SSTL_12, SSTL_135, SSTL_15 or SSTL_18 signaling\nLow RON (10 Ω typi;

恩XP

恩智浦