CAHCT138QWBQBRQ1中文资料德州仪器数据手册PDF规格书

1 Features

• Qualified for Automotive Applications

• EPIC (Enhanced-Performance Implanted CMOS)

Process

• Inputs Are TTL-Voltage Compatible

• Designed Specifically for High-Speed Memory

Decoders and Data-Transmission Systems

• Incorporates Three Enable Inputs to Simplify

Cascading and/or Data Reception

• Latch-Up Performance Exceeds 250mA Per JESD

17

• ESD Protection Exceeds 2000V Per MIL-STD-833,

Method 3015

2 Description

The SN74AHCT138Q 3-line to 8-line decoder/

demultiplexer is designed to be used in highperformance

memory-decoding and data-routing

applications that require very short propagation-delay

times. In high-performance memory systems, this

decoder can be used to minimize the effects of

system decoding. When employed with high-speed

memories utilizing a fast enable circuit, the delay

times of this decoder and the enable time of the

memory usually are less than the typical access time

of the memory. This means that the effective system

delay introduced by the decoder is negligible.