C167CS-LM中文资料英飞凌数据手册PDF规格书

Introduction

The rapidly growing area of embedded control applications is representing one of the most time-critical operating environments for today’s microcontrollers. Complex control algorithms have to be processed based on a large number of digital as well as analog input signals, and the appropriate output signals must be generated within a defined maximum response time. Embedded control applications also are often sensitive to board space, power consumption, and overall system cost.

Summary of Basic Features

The C167CS is an improved representative of the Infineon family of full featured 16-bit single-chip CMOS microcontrollers. It combines high CPU performance (up to 12.5/16.5 million instructions per second) with high peripheral functionality and means for power reduction.

Several key features contribute to the high performance of the C167CS (the indicated timings refer to a CPU clock of 25/33 MHz).

High Performance 16-bit CPU with Four-Stage Pipeline

• 80/60 ns minimum instruction cycle time, with most instructions executed in 1 cycle

• 400/300 ns multiplication (16-bit × 16-bit), 800/600 ns division (32-bit/16-bit)

• Multiple high bandwidth internal data buses

• Register based design with multiple variable register banks

• Single cycle context switching support

• 16 MBytes linear address space for code and data (Von Neumann architecture)

• System stack cache support with automatic stack overflow/underflow detection

Control Oriented Instruction Set with High Efficiency

• Bit, byte, and word data types

• Flexible and efficient addressing modes for high code density

• Enhanced boolean bit manipulation with direct addressability of 6 Kbits for peripheral control and user defined flags

• Hardware traps to identify exception conditions during runtime

• HLL support for semaphore operations and efficient data access

Integrated On-Chip Memory

• 3 KByte internal RAM for variables, register banks, system stack and code

• 8 KByte on-chip high-speed XRAM for variables, user stack and code

• 32 KByte on-chip ROM (not for ROMless devices)

External Bus Interface

• Multiplexed or demultiplexed bus configurations

• Segmentation capability and chip select signal generation

• 8-bit or 16-bit data bus

• Bus cycle characteristics selectable for five programmable address areas

16-Priority-Level Interrupt System

• 56 interrupt nodes with separate interrupt vectors

• 240/180 ns typical interrupt latency (400/300 ns maximum) in case of internal program execution

• Fast external interrupts

8-Channel Peripheral Event Controller (PEC)

• Interrupt driven single cycle data transfer

• Transfer count option (std. CPU interrupt after programmable number of PEC transfers)

• Eliminates overhead of saving and restoring system state for interrupt requests

Intelligent On-Chip Peripheral Subsystems

• 24-channel 10-bit A/D Converter with programmable conversion time (7.76 µs minimum), auto scan modes, channel injection mode

• Two 16-channel Capture/Compare Units with 2 independent time bases each, very flexible PWM unit/event recording unit with different operating modes, includes four 16-bit timers/counters, maximum resolution fCPU/8

• 4-channel PWM unit

• Two Multifunctional General Purpose Timer Units

GPT1: Three 16-bit timers/counters, maximum resolution fCPU/8

GPT2: Two 16-bit timers/counters, maximum resolution fCPU/4

• Asynchronous/Synchronous Serial Channels (USART) with baud rate generator, parity, framing, and overrun error detection

• High Speed Synchronous Serial Channel programmable data length and shift direction

• Two on-chip CAN Bus Modules, Rev. 2.0B active

• Real Time Clock

• Watchdog Timer with programmable time intervals

• Bootstrap Loader for flexible system initialization

111 IO Lines with Individual Bit Addressability

• Tri-stated in input mode

• Selectable input thresholds (not on all pins)

• Push/pull or open drain output mode

• Programmable port driver control

Different Temperature Ranges

• 0 to + 70 °C, – 40 to + 85 °C, – 40 to + 125 °C