ECL/PECL 첨 2 Divider

DESCRIPTION The AZ10/100EL32 is an integrated ÷2 divider. The reset pin is asynchronous and is asserted on the rising edge. Upon power-up, the internal flip-flop will attain a random logic state; the reset allows for the synchronization of multiple EL32’s in a system. The EL32 provides a VBB

文件：104.2 Kbytes 页数：6 Pages

AZM

ECL/PECL 첨 2 Divider

DESCRIPTION The AZ10/100EL32 is an integrated ÷2 divider. The reset pin is asynchronous and is asserted on the rising edge. Upon power-up, the internal flip-flop will attain a random logic state; the reset allows for the synchronization of multiple EL32’s in a system. The EL32 provides a VBB

文件：104.21 Kbytes 页数：6 Pages

ETCList of Unclassifed Manufacturers

未分类制造商

ECL/PECL 첨 2 Divider

DESCRIPTION The AZ10/100EL32 is an integrated ÷2 divider. The reset pin is asynchronous and is asserted on the rising edge. Upon power-up, the internal flip-flop will attain a random logic state; the reset allows for the synchronization of multiple EL32’s in a system. The EL32 provides a VBB

文件：104.21 Kbytes 页数：6 Pages

ETCList of Unclassifed Manufacturers

未分类制造商

ECL/PECL 첨 2 Divider

DESCRIPTION The AZ10/100EL32 is an integrated ÷2 divider. The reset pin is asynchronous and is asserted on the rising edge. Upon power-up, the internal flip-flop will attain a random logic state; the reset allows for the synchronization of multiple EL32’s in a system. The EL32 provides a VBB

文件：104.2 Kbytes 页数：6 Pages

AZM

ECL/PECL 첨 2 Divider

DESCRIPTION The AZ10/100EL32 is an integrated ÷2 divider. The reset pin is asynchronous and is asserted on the rising edge. Upon power-up, the internal flip-flop will attain a random logic state; the reset allows for the synchronization of multiple EL32’s in a system. The EL32 provides a VBB

文件：104.21 Kbytes 页数：6 Pages

ETCList of Unclassifed Manufacturers

未分类制造商

ECL/PECL 첨 2 Divider

DESCRIPTION The AZ10/100EL32 is an integrated ÷2 divider. The reset pin is asynchronous and is asserted on the rising edge. Upon power-up, the internal flip-flop will attain a random logic state; the reset allows for the synchronization of multiple EL32’s in a system. The EL32 provides a VBB

文件：104.2 Kbytes 页数：6 Pages

AZM

ECL/PECL ÷ 2 Divider

DESCRIPTION\nThe AZ10/100EL32 is an integrated ÷2 divider. The reset pin is asynchronous and is asserted on the rising edge. Upon power-up, the internal flip-flop will attain a random logic state; the reset allows for the synchronization of multiple EL32’s in a system.\nThe EL32 provides a VBB outpu • 510ps Propagation Delay\n• 3.0GHz Toggle Frequency\n• High Bandwidth Output Transitions\n• 75kΩ Internal Input Pulldown Resistors\n• Direct Replacement for ON Semiconductor MC10EL32 & MC100EL32;

Arizona

4.75 V-5.5 V, ECL/PECL 2 divider

Arizona