AM654x, AM652x Sitara™ Processors Silicon Revision 2.1

1 Features Processor cores: • Dual- or quad-core Arm® Cortex®-A53 microprocessor subsystem at up to 1.1 GHz – Up to two dual-core or two single-core Arm® Cortex®-A53 clusters with 512KB L2 cache including SECDED – Each A53 core has 32KB L1 ICache and 32K L1 DCache • Dual-core Arm® Cortex®

文件：6.84172 Mbytes 页数：284 Pages

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德州仪器

Sitara Processors

文件：3.37106 Mbytes 页数：299 Pages

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德州仪器

Processors Silicon Revision 1.0

文件：4.08534 Mbytes 页数：277 Pages

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德州仪器

丝印：AM6546BACDXA；Package：FCBGA；AM654x, AM652x Sitara™ Processors Silicon Revision 2.1

1 Features Processor cores: • Dual- or quad-core Arm® Cortex®-A53 microprocessor subsystem at up to 1.1 GHz – Up to two dual-core or two single-core Arm® Cortex®-A53 clusters with 512KB L2 cache including SECDED – Each A53 core has 32KB L1 ICache and 32K L1 DCache • Dual-core Arm® Cortex®

文件：6.84172 Mbytes 页数：284 Pages

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德州仪器

具有千兆位 PRU-ICSS 的四核 Arm® Cortex®-A53 和双核 Arm Cortex-R5F Sitara™ 处理器

AM654x and AM652x Sitara Arm applications processors are built to meet the complexprocessing needs of modern industrial embedded products.\nThe AM654x and AM652x devices combine four or two Arm Cortex-A53 cores with a dualCortex-R5F MCU subsystem which includes features intended to help customers ac • 处理器内核：\n• 每个 A53 内核具有 32KB L1 指令缓存和 32K L1 数据缓存\n• 每个 R5F 内核具有 16KB 指令缓存、16KB 数据缓存和 64KB RAM\n• 三个千兆位工业通信子系统 (PRU_ICSSG) \n• 支持两个 SGMII 端口• \n• 每个 PRU_ICSSG 具有 24 个 PWM\n• 增强跳闸控制 \n• 每个 PRU_ICSSG 具有 18 个 Σ-Δ 滤波器\n• 过流逻辑 \n• 每个 PRU_ICSSG 具有 6 个多协议位置编码器接口\n• 高达 2MB 的片上 L3 RAM（具有 SECDED）\n• 共享相干 3 级缓;

TI

德州仪器

AM654x, AM652x Sitara™ Processors Silicon Revision 2.1

1 Features Processor cores: • Dual- or quad-core Arm® Cortex®-A53 microprocessor subsystem at up to 1.1 GHz – Up to two dual-core or two single-core Arm® Cortex®-A53 clusters with 512KB L2 cache including SECDED – Each A53 core has 32KB L1 ICache and 32K L1 DCache • Dual-core Arm® Cortex®

文件：6.84172 Mbytes 页数：284 Pages

TI

德州仪器