ADS6616A4A-7中文资料威刚科技数据手册PDF规格书

General Description

The ADS6616A4A are four-bank Synchronous DRAMs organized as 1,048,576 words x 16 bits x 4 banks, Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle.

Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth high performance memory system applications

特性 Features

• JEDEC standard LVTTL 3.3V power supply

• MRS Cycle with address key programs

   -CAS Latency (2 & 3)

   -Burst Length (1,2,3,8,& full page)

   -Burst Type (sequential & Interleave)

• 4 banks operation

• All inputs are sampled at the positive edge of the system clock

• Burst Read single write operation

• Auto & Self refresh

• 4096 refresh cycle

• DQM for masking

• Package:54-pins 400 mil TSOP-Type II