3.1 GHz to 4.2 GHz, Receiver Front End

GENERAL DESCRIPTION The ADRF5534 is an integrated RF, front-end multichip module designed for time division duplex (TDD) applications. The device operates from 3.1 GHz to 4.2 GHz. The ADRF5534 is configured with an LNA and a high-power, silicon, SPDT switch. In the receive operation at 3.6 GH

文件：685 Kbytes 页数：11 Pages

AD

亚德诺

3.1 GHz to 4.2 GHz, Receiver Front End

FEATURES ► Integrated RF front end ► LNA and high-power silicon SPDT switch ► On-chip bias and matching ► Single-supply operation ► Gain: 35.5 dB typical at 3.6 GHz ► Gain flatness: 1.5 dB at 25°C across 400 MHz bandwidth ► Low noise figure: 1.3 dB typical at 3.6 GHz ► Low insertion loss:

文件：686.07 Kbytes 页数：11 Pages

AD

亚德诺

3.1 GHz 至 4.2 GHz，接收器前端

ADRF5534 是一款集成 RF 的前端多芯片模块，设计用于时分双工 (TDD) 应用。该套件的工作频率为 3.1 GHz 至 4.2 GHz。ADRF5534 配置有 LNA 和一个大功率硅 SPDT 开关。\n\n 在 3.6 GHz 的接收过程中，LNA 提供 1.3 dB 的低噪声指数 (NF) 和 35.5 dB 的高增益，并且具有 −4 dBm 的三阶交调截点 (IIP3)。\n\n 在发射过程中，该开关提供 0.8 dB 的低插入损耗，并在整个生命周期内处理 37 dBm 的长期演进 (LTE) 平均功率（8 dB 峰值至平均值比 (PAR)），而在单一事件 • 集成式 RF 前端\n• LNA 和高功率硅 SPDT 开关\n• 片内偏置和匹配\n• 单电源供电\n• 增益：3.6 GHz 时为 35.5 dB（典型值）\n• 增益平坦度：25°C 下为 1.5 dB（400 MHz 带宽）\n• 低噪声指数：3.6 GHz 时为 1.3 dB（典型值）\n• 低插入损耗：3.6 GHz 时为 0.8 dB（典型值）;

ADI

亚德诺

3.1 GHz to 4.2 GHz, Receiver Front End

FEATURES ► Integrated RF front end ► LNA and high-power silicon SPDT switch ► On-chip bias and matching ► Single-supply operation ► Gain: 35.5 dB typical at 3.6 GHz ► Gain flatness: 1.5 dB at 25°C across 400 MHz bandwidth ► Low noise figure: 1.3 dB typical at 3.6 GHz ► Low insertion loss:

文件：686.07 Kbytes 页数：11 Pages

AD

亚德诺

3.1 GHz to 4.2 GHz, Receiver Front End

FEATURES ► Integrated RF front end ► LNA and high-power silicon SPDT switch ► On-chip bias and matching ► Single-supply operation ► Gain: 35.5 dB typical at 3.6 GHz ► Gain flatness: 1.5 dB at 25°C across 400 MHz bandwidth ► Low noise figure: 1.3 dB typical at 3.6 GHz ► Low insertion loss:

文件：686.07 Kbytes 页数：11 Pages

AD

亚德诺

3.1 GHz to 4.2 GHz, Receiver Front End

GENERAL DESCRIPTION The ADRF5534 is an integrated RF, front-end multichip module designed for time division duplex (TDD) applications. The device operates from 3.1 GHz to 4.2 GHz. The ADRF5534 is configured with an LNA and a high-power, silicon, SPDT switch. In the receive operation at 3.6 GH

文件：685 Kbytes 页数：11 Pages

AD

亚德诺

3.1 GHz to 4.2 GHz, Receiver Front End

GENERAL DESCRIPTION The ADRF5534 is an integrated RF, front-end multichip module designed for time division duplex (TDD) applications. The device operates from 3.1 GHz to 4.2 GHz. The ADRF5534 is configured with an LNA and a high-power, silicon, SPDT switch. In the receive operation at 3.6 GH

文件：685 Kbytes 页数：11 Pages

AD

亚德诺

3.1 GHz to 4.2 GHz, Receiver Front End

FEATURES ► Integrated RF front end ► LNA and high-power silicon SPDT switch ► On-chip bias and matching ► Single-supply operation ► Gain: 35.5 dB typical at 3.6 GHz ► Gain flatness: 1.5 dB at 25°C across 400 MHz bandwidth ► Low noise figure: 1.3 dB typical at 3.6 GHz ► Low insertion loss:

文件：686.07 Kbytes 页数：11 Pages

AD

亚德诺

3.1 GHz to 4.2 GHz, Receiver Front End

FEATURES ► Integrated RF front end ► LNA and high-power silicon SPDT switch ► On-chip bias and matching ► Single-supply operation ► Gain: 35.5 dB typical at 3.6 GHz ► Gain flatness: 1.5 dB at 25°C across 400 MHz bandwidth ► Low noise figure: 1.3 dB typical at 3.6 GHz ► Low insertion loss:

文件：686.07 Kbytes 页数：11 Pages

AD

亚德诺

3.1 GHz to 4.2 GHz, Receiver Front End

GENERAL DESCRIPTION The ADRF5534 is an integrated RF, front-end multichip module designed for time division duplex (TDD) applications. The device operates from 3.1 GHz to 4.2 GHz. The ADRF5534 is configured with an LNA and a high-power, silicon, SPDT switch. In the receive operation at 3.6 GH

文件：685 Kbytes 页数：11 Pages

AD

亚德诺