AD9675集成电路（IC）的模拟前端（AFE）规格书PDF中文资料

AD9675属于集成电路（IC）的模拟前端（AFE）。由亚德诺半导体技术有限公司制造生产的AD9675模拟前端（AFE）模拟前端 (AFE) 是一种用于信号调节的半导体器件，由模拟放大器、运算放大器、滤波器和集成电路构成。这种可配置功能块能连接各种传感器。分辨率范围从 8 位至 42 位不等，通道数范围为 1 至 256 个。

GENERAL DESCRIPTION

The AD9675 is designed for low cost, low power, small size, and ease of use for medical ultrasound. It contains eight channels of a variable gain amplifier (VGA) with a low noise preamplifier (LNA), a CW harmonic rejection I/Q demodulator with programmable phase rotation, an anti-aliasing filter (AAF), an analog-to-digital converter (ADC), a digital highpass filter and an RF decimation by 2. Each channel features a maximum gain of up to 52 dB, a fully differential signal path, and an active input preamplifier termination. The channel is optimized for high dynamic performance and low power in applications where a small package size is critical.

The LNA has a single-ended-to-differential gain that is selectable through the SPI. Assuming a 15 MHz noise bandwidth (NBW) and a 21.6 dB LNA gain, the LNA input SNR is 94 dB. In CW Doppler mode, each LNA output drives an I/Q demodulator that has independently programmable phase rotation with 16 phase settings.

Power-down of individual channels is supported to increase battery life for portable applications. Standby mode allows quick power-up for power cycling. In CW Doppler operation, the VGA, AAF, and ADC are powered down. The ADC contains several features designed to maximize flexibility and minimize system cost, such as a programmable clock, data alignment, and programmable digital test pattern generation. The digital test patterns include built-in fixed patterns, built-in pseudo random patterns, and custom user-defined test patterns entered via the serial port interface.

FEATURES

8 channels of LNA, VGA, AAF, ADC, and digital RF decimator

Low power: 150 mW per channel, TGC mode, 40 MSPS;

65mW per channel, CW mode; <30mW at power-up

10 mm × 10 mm, 144-ball CSP-BGA

TGC channel input-referred noise: 0.8 nV/√Hz, max gain

Flexible power-down modes

Fast recovery from low power standby mode: <2 μs

Overload recovery: <10 ns

Low noise preamplifier (LNA)

Input-referred noise: 0.78 nV/√Hz, gain = 21.6 dB

Programmable gain: 15.6 dB/17.9 dB/21.6 dB

0.1 dB compression: 1000 mV p-p/750 mV p-p/450 mV p-p

Flexible active input impedance matching

Variable gain amplifier (VGA)

Attenuator range: 45dB, Linear-in-dB gain control

Postamp gain (PGA): 21 dB/24 dB/27 dB/30 dB

Antialiasing filter (AAF)

Programmable second-order LPF from 8 MHz to 18 MHz or

13.5MHz to 30MHz and HPF

Analog-to-digital converter (ADC)

SNR: 75dB, 14 bits up to 125 MSPS

JESD204B Subclass 0 coded serial digital outputs

CW mode harmonic rejection I/Q demodulator

Individual programmable phase rotation

Output dynamic range per channel: >160 dBc/√Hz

Output-referred SNR: 156 dBc/√Hz, 1 kHz offset, −3dBFS

RF digital high-pass filter and decimation by 2