Low Power, 8-/16-Channel, 31.25 kSPS, 24-Bit, Highly Integrated Sigma-Delta ADC

GENERAL DESCRIPTION Fast settling, highly accurate, low power, 8-/16-channel, multiplexed ADC for low bandwidth input signals with integrated input buffers. Integrated precision, 2.5 V, low drift (3.5 ppm/°C), band gap reference and integrated oscillator. FEATURES Low power, 8-/16-channel,

文件：1.08993 Mbytes 页数：64 Pages

AD

亚德诺

24-Bit, 250 kSPS, Sigma-Delta ADC with 20 us Settling and True Rail-to-Rail Buffers

GENERAL DESCRIPTION The AD7175-2 is a low noise, fast settling, multiplexed, 2-/4-channel (fully/pseudo differential) Σ-Δ analog-to-digital converter (ADC) for low bandwidth inputs. It has a maximum channel scan rate of 50 kSPS (20 µs) for fully settled data. The output data rates range from 5 SP

文件：1.20509 Mbytes 页数：63 Pages

AD

亚德诺

24-Bit, 250 kSPS, Sigma-Delta ADC with 20 us Settling and True Rail-to-Rail Buffers

GENERAL DESCRIPTION The AD7175-2 is a low noise, fast settling, multiplexed, 2-/4-channel (fully/pseudo differential) Σ-Δ analog-to-digital converter (ADC) for low bandwidth inputs. It has a maximum channel scan rate of 50 kSPS (20 µs) for fully settled data. The output data rates range from 5 SP

文件：1.20509 Mbytes 页数：63 Pages

AD

亚德诺

24-Bit, 250 kSPS, Sigma-Delta ADC with 20 us Settling and True Rail-to-Rail Buffers

GENERAL DESCRIPTION The AD7175-2 is a low noise, fast settling, multiplexed, 2-/4-channel (fully/pseudo differential) Σ-Δ analog-to-digital converter (ADC) for low bandwidth inputs. It has a maximum channel scan rate of 50 kSPS (20 µs) for fully settled data. The output data rates range from 5 SP

文件：1.20509 Mbytes 页数：63 Pages

AD

亚德诺

24-Bit, 250 kSPS, Sigma-Delta ADC with 20 us Settling and True Rail-to-Rail Buffers

GENERAL DESCRIPTION The AD7175-2 is a low noise, fast settling, multiplexed, 2-/4-channel (fully/pseudo differential) Σ-Δ analog-to-digital converter (ADC) for low bandwidth inputs. It has a maximum channel scan rate of 50 kSPS (20 µs) for fully settled data. The output data rates range from 5 SP

文件：1.20509 Mbytes 页数：63 Pages

AD

亚德诺

24-Bit, 8-/16-Channel, 250 kSPS, Sigma- Delta ADC with True Rail-to-Rail Buffers

GENERAL DESCRIPTION The AD7175-8 is a low noise, fast settling, multiplexed, 8-/16-channel (fully/pseudo differential) Σ-Δ analog-to-digital converter (ADC) for low bandwidth inputs. It has a maximum channel scan rate of 50 kSPS (20 µs) for fully settled data. The output data rates range from 5 S

文件：1.08831 Mbytes 页数：64 Pages

AD

亚德诺

24-Bit, 8-/16-Channel, 250 kSPS, Sigma- Delta ADC with True Rail-to-Rail Buffers

GENERAL DESCRIPTION The AD7175-8 is a low noise, fast settling, multiplexed, 8-/16-channel (fully/pseudo differential) Σ-Δ analog-to-digital converter (ADC) for low bandwidth inputs. It has a maximum channel scan rate of 50 kSPS (20 µs) for fully settled data. The output data rates range from 5 S

文件：1.08831 Mbytes 页数：64 Pages

AD

亚德诺

24-Bit, 8-/16-Channel, 250 kSPS, Sigma- Delta ADC with True Rail-to-Rail Buffers

GENERAL DESCRIPTION The AD7175-8 is a low noise, fast settling, multiplexed, 8-/16-channel (fully/pseudo differential) Σ-Δ analog-to-digital converter (ADC) for low bandwidth inputs. It has a maximum channel scan rate of 50 kSPS (20 µs) for fully settled data. The output data rates range from 5 S

文件：1.08831 Mbytes 页数：64 Pages

AD

亚德诺

24-Bit, 8-/16-Channel, 250 kSPS, Sigma- Delta ADC with True Rail-to-Rail Buffers

GENERAL DESCRIPTION The AD7175-8 is a low noise, fast settling, multiplexed, 8-/16-channel (fully/pseudo differential) Σ-Δ analog-to-digital converter (ADC) for low bandwidth inputs. It has a maximum channel scan rate of 50 kSPS (20 µs) for fully settled data. The output data rates range from 5 S

文件：1.08831 Mbytes 页数：64 Pages

AD

亚德诺

The AD7176-2 is a fast settling, highly accurate, high resolution, multiplexed 誇-? analog-to-digital converter (ADC) for low band-width input signals.

GENERAL DESCRIPTION The AD7176-2 is a fast settling, highly accurate, high resolution, multiplexed Σ-Δ analog-to-digital converter (ADC) for low bandwidth input signals. Its inputs can be configured as two fully differential or four pseudo differential inputs via the integrated crosspoint multipl

文件：959.6 Kbytes 页数：68 Pages

AD

亚德诺