AD632S集成电路（IC）的模拟乘法器、除法器规格书PDF中文资料

AD632S属于集成电路（IC）的模拟乘法器、除法器。由亚德诺半导体技术有限公司制造生产的AD632S模拟乘法器、除法器模拟乘法器获取两个或更多模拟信号，并产生这些信号的乘积或乘积之和的输出。此类电路可用于实现相关计算功能，例如计算平方（对两个输入都施加相同的信号）和平方根。应用可能包括可变增益放大器、环形调制器、乘积检测器、混频器、增益控制、真 RMS 转换器和脉冲幅度调制器 (PAM)。

GENERAL DESCRIPTION

The AD632 is an internally trimmed monolithic four-quadrant multiplier/divider. The AD632B has a maximum multiplying error of ±0.5 without external trims.

FEATURES

Pretrimmed to ±0.5 maximum 4-quadrant error

All inputs (X, Y, and Z) differential, high impedance for

[(X1 − X2)(Y1 − Y2)/10] + Z2 transfer function

Scale-factor adjustable to provide up to ×10 gain

Low noise design: 90 mV rms, 10 Hz to 10 kHz

Low cost, monolithic construction

Excellent long-term stability

APPLICATIONS

High quality analog signal processing

Differential ratio and percentage computations

Algebraic and trigonometric function synthesis

Accurate voltage controlled oscillators and filters