晶体管

JSCJ

长晶科技

1.8 V, 6 LVDS/12 CMOS Outputs Low Power Clock Fanout Buffer

CIRCUIT DESCRIPTION The circuit in Figure 1 was constructed by connecting the respective evaluation boards for the individual products. Connections were made with matched cable lengths. The first of three basic requirements to synchronize multiple AD9910’s is to provide a co-incident reference

文件：524.01 Kbytes 页数：16 Pages

AD

亚德诺

1.8 V, 6 LVDS/12 CMOS Outputs Low Power Clock Fanout Buffer

文件：468.98 Kbytes 页数：15 Pages

AD

亚德诺

Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers

CIRCUIT DESCRIPTION The circuit in Figure 1 was constructed by connecting the respective evaluation boards for the individual products. Connections were made with matched cable lengths. The first of three basic requirements to synchronize multiple AD9910’s is to provide a co-incident reference

文件：390.99 Kbytes 页数：3 Pages

AD

亚德诺