8V19N478数据手册集成电路（IC）的时钟发生器PLL频率合成器规格书PDF

描述 Description

The 8V19N478 is a fully integrated FemtoClock NG jitter attenuator and clock synthesizer designed as a high-performance clock solution for conditioning and frequency/phase management of 10/40/100/400 Gigabit-Ethernet line cards. The device is optimized to deliver excellent phase noise performance as required to drive physical layer devices, and provides the clean clock frequencies of 625MHz, 500MHz, 312.5MHz, 250MHz, 156.25MHz, and 125MHz. A two-stage PLL architecture supports both jitter attenuation and frequency multiplication. The first stage PLL is the jitter attenuator, and uses an external VCXO for best possible phase noise characteristics. The second stage PLL locks on the VCXO-PLL output signal, and synthesizes the target frequency. This PLL has a VCO circuit at 2500MHz. The 8V19N478 generates the output clock signals from the VCO by frequency division. Four independent frequency dividers are available; three support integer-divider ratios, and one integer as well as fractional-divider ratios. Delay circuits can be used for achieving alignment and controlled phase delay between clock signals. The two redundant inputs are monitored for activity. Four selectable clock switching modes are provided to handle clock input failure scenarios. Auto-lock, individually programmable output frequency dividers, and phase adjustment capabilities are added for flexibility. The device is configured through an I²C interface and reports lock and signal loss status in internal registers and via a lock detect (LOCK) output. Internal status bit changes can also be reported via the nINT output. The device is ideal for driving converter circuits in wireless infrastructure, radar/imaging, and instrumentation/medical applications. The device is a member of the high-performance clock family from IDT.

For information regarding evaluation boards and material, please contact your local IDT sales representative.

特性 Features

• High-performance clock RF-PLL
• Optimized for low phase noise: -153dBc/Hz (1MHz offset; 156.25MHz clock)
• Integrated phase noise (12kHz–20MHz) of 75fs RMS typ.
• Dual-PLL architecture
• 1st–PLL stage with external VCXO for clock jitter attenuation
• 2nd–PLL stage with internal FemtoClockNG PLL at 2500MHz

• 6 output banks with a total of 12 outputs, organized in:
• Two clock banks with one integer frequency divider and three differential outputs
• Two clock banks with one integer frequency divider and two differential outputs
• One clock bank with one fractional output divider and one differential output
• One VCXO-PLL output bank with one selectable LVDS/two LVCMOS outputs

• Four output banks contain a phase delay circuit with steps of the VCO clock period (400ps)
• Supported clock output frequencies include: 
• from the integer dividers: 2500, 1250, 625, 500, 312.5, 250, 156.25 and 125MHz
• from the fractional divider: 80–300MHz

• Low-power LVPECL/LVDS outputs support configurable signal amplitude, DC and AC coupling and LVPECL, LVDS line terminations techniques
• Redundant input clock architecture which supports two inputs, individual input signal monitor, digital holdover, manual & automatic clock selection, and Hitless switching
• Package: 11 x 11 mm, 1mm ball pitch 100-FPBGA
• Temperature range: -40°C to +85°C