Low Skew, 2:1 LVPECL MUX with 1:8 Fanout and Internal Termination

Features • Three output banks, consisting of eight LVPECL output pairs total • INx, nINx inputs can accept the following differential input levels: LVPECL, LVDS, CML • Selectable output divider values of ÷1, ÷2 and ÷4 • Maximum output frequency: 1.5GHz • Maximum input frequency: 3GHz • Bank

文件：625.18 Kbytes 页数：24 Pages

RENESAS

瑞萨

Low Skew, 2:1 LVPECL MUX with 1:8 Fanout and Internal Termination

文件：430.98 Kbytes 页数：23 Pages

IDT

丝印：ICS89202BIL；Package：VFQFN；Low Skew, 2:1 LVPECL MUX with 1:8 Fanout and Internal Termination

Features • Three output banks, consisting of eight LVPECL output pairs total • INx, nINx inputs can accept the following differential input levels: LVPECL, LVDS, CML • Selectable output divider values of ÷1, ÷2 and ÷4 • Maximum output frequency: 1.5GHz • Maximum input frequency: 3GHz • Bank

文件：625.18 Kbytes 页数：24 Pages

RENESAS

瑞萨

丝印：ICS89202BIL；Package：VFQFN；Low Skew, 2:1 LVPECL MUX with 1:8 Fanout and Internal Termination

Features • Three output banks, consisting of eight LVPECL output pairs total • INx, nINx inputs can accept the following differential input levels: LVPECL, LVDS, CML • Selectable output divider values of ÷1, ÷2 and ÷4 • Maximum output frequency: 1.5GHz • Maximum input frequency: 3GHz • Bank

文件：625.18 Kbytes 页数：24 Pages

RENESAS

瑞萨

丝印：ICS89202BIL；Package：VFQFN；Low Skew, 2:1 LVPECL MUX with 1:8 Fanout and Internal Termination

Features • Three output banks, consisting of eight LVPECL output pairs total • INx, nINx inputs can accept the following differential input levels: LVPECL, LVDS, CML • Selectable output divider values of ÷1, ÷2 and ÷4 • Maximum output frequency: 1.5GHz • Maximum input frequency: 3GHz • Bank

文件：625.18 Kbytes 页数：24 Pages

RENESAS

瑞萨

丝印：ICS89202BIL；Package：VFQFN；Low Skew, 2:1 LVPECL MUX with 1:8 Fanout and Internal Termination

Features • Three output banks, consisting of eight LVPECL output pairs total • INx, nINx inputs can accept the following differential input levels: LVPECL, LVDS, CML • Selectable output divider values of ÷1, ÷2 and ÷4 • Maximum output frequency: 1.5GHz • Maximum input frequency: 3GHz • Bank

文件：625.18 Kbytes 页数：24 Pages

RENESAS

瑞萨

丝印：ICS89202BIL；Package：VFQFN；Low Skew, 2:1 LVPECL MUX with 1:8 Fanout and Internal Termination

文件：430.98 Kbytes 页数：23 Pages

IDT

丝印：ICS89202BIL；Package：VFQFN；Low Skew, 2:1 LVPECL MUX with 1:8 Fanout and Internal Termination

文件：430.98 Kbytes 页数：23 Pages

IDT

Low Skew,2:1 LVPECL MUX With 1:8 Fanout And Internal Termination

The 8S89202I is a high speed 1-to-8 Differential-to-LVPECL Clock Divider and is part of the high performance clock solutions from IDT. The 8S89202I is optimized for high speed and very low output skew, making it suitable for use in demanding applications such as SONET, 1 Gigabit and 10 Gigabit Ether • Three output banks, consisting of eight LVPECL output pairs total\n• Selectable output divider values of ÷1, ÷2 and ÷4\n• Maximum input frequency: 3GHz\n• Part-to-part skew: 200ps (typical)\n• Propagation delay: 900ps (typical)\n• -40°C to 85°C ambient operating temperature\n• Available in lead-fr;

Renesas

瑞萨

Package：32-VFQFN 裸露焊盘；包装：托盘 类别：集成电路（IC） 时钟缓冲器，驱动器 描述：CLOCK SYNTHESIZE/GENERATOR/PLL

Renesas Electronics America Inc