8A34004E-DDDNBG8中文资料瑞萨数据手册PDF规格书

Features

▪ Two independent timing channels

• Each can act as a frequency synthesizer, jitter attenuator,

Digitally Controlled Oscillator (DCO), or Digital Phase Lock

Loop (DPLL)

• DPLLs generate telecom compliant clocks

▪ Compliant with ITU-T G.8262 for Synchronous Ethernet

▪ Compliant with legacy SONET/SDH and PDH

requirements

• DPLL Digital Loop Filters (DLFs) are programmable with cut

off frequencies from 12µHz to 22kHz

• DPLL/DCO channels share frequency information using the

Combo Bus to simplify compliance with ITU-T G.8273.2

• Switching between DPLL and DCO modes is hitless and

dynamic

▪ Automatic reference switching between DCO and DPLL

modes to simplify support for an external phase/time input

interface in a T-BC

• Generates output frequencies that are independent of input

frequencies via a Fractional Output Divider (FOD)

• Each FOD supports output phase tuning with 1ps resolution

▪ 4 Differential / 8 LVCMOS outputs

• Frequencies from 0.5Hz to 1GHz (250MHz for LVCMOS)

• Jitter below 150fs RMS (10kHz to 20MHz)

• LVCMOS, LVDS, LVPECL, HCSL, CML, SSTL, and HSTL

output modes supported

• Differential output swing is selectable: 400mV / 650mV /

800mV / 910mV

• Independent output voltages of 3.3V, 2.5V, or 1.8V

• LVCMOS additionally supports 1.5V or 1.2V

• The clock phase of each output is individually programmable

in 1ns to 2ns steps with a total range of ±180°

▪ 2 differential / 4 single-ended clock inputs

• Support frequencies from 0.5Hz to 1GHz

• Any input can be mapped to any or all of the timing channels

• Redundant inputs frequency independent of each other

• Any input can be designated as external frame/sync pulse of

PPES (pulse per even second), 1 PPS (Pulse per Second),

5PPS, 10 PPS, 50Hz, 100Hz, 1 kHz, 2 kHz, 4kHz, and 8kHz

associated with a selectable reference clock input

• Per-input programmable phase offset of up to ±1.638s in

1ps steps

▪ Reference monitors qualify/disqualify references depending on

LOS, activity, frequency monitoring, and/or LOS input pins

• Loss of Signal (LOS) input pins (via GPIOs) can be assigned

to any input clock reference

▪ Automatic reference selection state machines select the active

reference for each DPLL based on the reference monitors,

priority tables, revertive / non-revertive, and other

programmable settings

▪ System APLL operates from fundamental-mode crystal: 25MHz

to 54MHz or from a crystal oscillator

▪ System DPLL accepts an XO, TCXO, or OCXO operating at

virtually any frequency from 1MHz to 150MHz

▪ DPLLs can be configured as DCOs to synthesize Precision

Time Protocol (PTP) / IEEE 1588 clocks

• DCOs generate PTP based clocks with frequency resolution

less than 1.11 × 10-16

▪ DPLL Phase detectors can be used as Time-to-Digital

Converters (TDC) with precision below 1ps

▪ Supports 1MHz I2

C or 50MHz SPI serial processor ports

▪ The device can configure itself automatically after reset via:

• Internal customer definable One-Time Programmable

memory with up to 16 different configurations

• Standard external I2

C EPROM via separate I2

C Master Port

▪ 1149.1 JTAG Boundary Scan

▪ 7 × 7 mm 48-VFQFPN package

Description

The 8A34004 is a Synchronization Management Unit (SMU) for packet based and physical layer based equipment synchronization. The

8A34004 is a highly integrated device that provides tools to manage timing references, clock sources, and timing paths for IEEE 1588

and Synchronous Ethernet (SyncE) based clocks. The PLL channels can act independently as frequency synthesizers, jitter attenuators,

Digitally Controlled Oscillators (DCO) or Digital Phase Lock Loops (DPLL).

The 8A34004 supports multiple independent timing paths that can each be configured as a DPLL or as a DCO. Input-to-input,

input-to-output, and output-to-output phase skew can all be precisely managed. The device outputs low-jitter clocks that can directly

synchronize interfaces such as 100GBASE-R, 40GBASE-R, 10GBASE-R, and 10GBASE-W and lower-rate Ethernet interfaces, as well

as SONET/SDH and PDH interfaces and IEEE 1588 Time Stamp Units (TSUs).

The internal System APLL must be supplied with a low phase noise reference clock with frequency between 25MHz and 54MHz. The

output of the System APLL is used for clock synthesis by all of the Fractional Output Dividers (FODs) in the device. The System APLL

reference can come from an external crystal oscillator connected to the OSCI pin or from an internal oscillator that uses a crystal

connected between the OSCI and OSCO pins