83948I中文资料瑞萨数据手册PDF规格书

特性 Features

• Twelve LVCMOS/LVTTL outputs

• Selectable differential CLK/nCLK or LVCMOS/LVTTL clock

input

• CLK/nCLK pair can accept the following differential

input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL

• LVCMOS_CLK supports the following input types: LVCMOS,

LVTTL

• Maximum output frequency: 250MHz

• Output skew: 350ps (maximum)

• Part-to-part skew: 1.5ns (maximum)

• 3.3V core, 3.3V output

• -40°C to 85°C ambient operating temperature

• Available in lead-free (RoHS 6) package

• For drop in replacement part use 83948i-147