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74LVTH162245GRE4中文资料德州仪器数据手册PDF规格书

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厂商型号

74LVTH162245GRE4

功能描述

3.3-V ABT 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

丝印标识

LVTH162245

封装外壳

TSSOP(DGG)

文件大小

502 Kbytes

页面数量

19

生产厂商

TI

中文名称

德州仪器

网址

网址

数据手册

下载地址一下载地址二到原厂下载

更新时间

2025-11-2 23:00:00

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74LVTH162245GRE4规格书详情

FEATURES

· Members of the Texas Instruments Widebus™

Family

· A-Port Outputs Have Equivalent 22-W Series

Resistors, So No External Resistors Are

Required

· Support Mixed-Mode Signal Operation (5-V

Input and Output Voltages With 3.3-V VCC)

· Support Unregulated Battery Operation Down

to 2.7 V

· Typical VOLP (Output Ground Bounce) <0.8 V

at VCC = 3.3 V, TA = 25°C

· Ioff and Power-Up 3-State Support Hot

Insertion

· Bus Hold on Data Inputs Eliminates the Need

for External Pullup/Pulldown Resistors

· Distributed VCC and GND Pins Minimize

High-Speed Switching Noise

· Flow-Through Architecture Optimizes PCB

Layout

· Latch-Up Performance Exceeds 500 mA Per

JESD 17

· ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

– 1000-V Charged-Device Model (C101)

DESCRIPTION/ORDERING INFORMATION

The 'LVTH162245 devices are 16-bit (dual-octal) noninverting 3-state transceivers designed for low-voltage

(3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.

These devices can be used as two 8-bit transceivers or one 16-bit transceiver. The devices allow data

transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the

direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses

are effectively isolated.

The logic levels of the direction-control (DIR) input and the output-enable (OE) input activate either the B-port

outputs or the A-port outputs or place both output ports into the high-impedance mode. The device transmits

data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when

the A-port outputs are activated. The input circuitry on both A and B ports is always active and must have a logic

HIGH or LOW level applied to prevent excess ICC and ICCZ.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown

resistors with the bus-hold circuitry is not recommended.

The A-port outputs, which are designed to source or sink up to 12 mA, include equivalent 22-W series resistors

to reduce overshoot and undershoot.

产品属性

  • 型号:

    74LVTH162245GRE4

  • 功能描述:

    总线收发器 3.3V ABT 16B 总线收发器

  • RoHS:

  • 制造商:

    Fairchild Semiconductor

  • 逻辑类型:

    CMOS

  • 逻辑系列:

    74VCX

  • 每芯片的通道数量:

    16

  • 输入电平:

    CMOS

  • 输出电平:

    CMOS

  • 输出类型:

    3-State

  • 高电平输出电流:

    - 24 mA

  • 低电平输出电流:

    24 mA

  • 传播延迟时间:

    6.2 ns

  • 电源电压-最大:

    2.7 V, 3.6 V

  • 电源电压-最小:

    1.65 V, 2.3 V

  • 最大工作温度:

    + 85 C

  • 封装/箱体:

    TSSOP-48

  • 封装:

    Reel

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