Dual buffer gate

The 74LVC2G34-Q100 provides two buffers.\n Inputs can be driven from either 3.3 V or 5 V devices. These features allow the use of these devices in a mixed 3.3 V and 5 V environment.\n This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the • Automotive product qualification in accordance with AEC-Q100 (Grade 1)• Specified from -40 °C to +85 °C and from -40 °C to +125 °C\n\n• Wide supply voltage range from 1.65 V to 5.5 V\n• 5 V tolerant inputs for interfacing with 5 V logic\n• High noise immunity\n• Complies with JEDEC standard:• JESD;

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丝印：YA；Package：SC-88；Dual buffer gate

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Package：6-TSSOP，SC-88，SOT-363；包装：管件 类别：集成电路（IC） 缓冲器，驱动器，接收器，收发器 描述：IC BUF NON-INVERT 5.5V 6TSSOP

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