Hex D-type flip-flop with reset; positive-edge trigger

DESCRIPTION The 74LV174 is a low–voltage Si–gate CMOS device and is pin and function compatible with the 74HC/HCT174. FEATURES • Wide operating voltage: 1.0 to 5.5V • Optimized for Low Voltage applications: 1.0 to 3.6V • Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V • Typical VO

文件：121.78 Kbytes 页数：14 Pages

PHI

飞利浦

Hex D-type flip-flop with reset; positive-edge trigger

DESCRIPTION The 74LV174 is a low–voltage Si–gate CMOS device and is pin and function compatible with the 74HC/HCT174. FEATURES • Wide operating voltage: 1.0 to 5.5V • Optimized for Low Voltage applications: 1.0 to 3.6V • Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V • Typical VO

文件：121.78 Kbytes 页数：14 Pages

PHI

飞利浦

Hex D-type Flip-Flops with Clear

Description This device contains 6 master-slave flip-flops with a common clock and common clear. Data on the D input having the specified setup and hold times is transferred to the Q output on the low to high transition of the clock input. The clear input when low, sets all outputs to a low state

文件：64 Kbytes 页数：15 Pages

HitachiHitachi Semiconductor

日立日立公司

Hex D-type flip-flop with reset; positive edge-trigger

The 74LV174 is a low–voltage Si–gate CMOS device and is pin and function compatible with the 74HC/HCT174. The device is useful for applications requiring true outputs only and clock and master reset inputs that are common to all storage elements. • Output voltage levels are compatible with input

文件：50.38 Kbytes 页数：6 Pages

INTEGRAL

Integral Corp.

Hex D-type flip-flop with reset; positive edge-trigger

The 74LV174 is a low–voltage Si–gate CMOS device and is pin and function compatible with the 74HC/HCT174. The device is useful for applications requiring true outputs only and clock and master reset inputs that are common to all storage elements. • Output voltage levels are compatible with input

文件：50.38 Kbytes 页数：6 Pages

INTEGRAL

Integral Corp.