Dual JK flip-flop with set and reset; positive-edge trigger

DESCRIPTION The 74LV109 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT109. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. FEATURES • Optimized for low voltage applications: 1.0 to 3.6 V •

文件：124.88 Kbytes 页数：12 Pages

PHI

飞利浦

Dual JK flip-flop with set and reset; positive-edge trigger

DESCRIPTION The 74LV109 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT109. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. FEATURES • Optimized for low voltage applications: 1.0 to 3.6 V •

文件：124.88 Kbytes 页数：12 Pages

PHI

飞利浦

Dual JK flip-flop with set and reset; positive-edge trigger

DESCRIPTION The 74LV109 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT109. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. FEATURES • Optimized for low voltage applications: 1.0 to 3.6 V •

文件：124.88 Kbytes 页数：12 Pages

PHI

飞利浦

Dual JK flip-flop with set and reset; positive-edge trigger

DESCRIPTION The 74LV109 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT109. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. FEATURES • Optimized for low voltage applications: 1.0 to 3.6 V •

文件：124.88 Kbytes 页数：12 Pages

PHI

飞利浦