74LV07AT集成电路（IC）的缓冲器驱动器接收器收发器规格书PDF中文资料

厂商型号	74LV07AT
参数属性	74LV07AT 封装/外壳为14-TSSOP（0.173"，4.40mm 宽）；包装为卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带；类别为集成电路（IC）的缓冲器驱动器接收器收发器；产品描述：IC BUF NON-INVERT 5.5V 14TSSOP
功能描述	Hex buffer with open-drain outputs
封装外壳	14-TSSOP（0.173"，4.40mm 宽）
文件大小	727.31 Kbytes
页面数量	12 页
生产厂商	NEXPERIA
中文名称	安世
网址	网址
数据手册	下载地址一下载地址二到原厂下载
更新时间	2025-11-2 16:38:00
人工找货	74LV07AT价格和库存，欢迎联系客服免费人工找货

1. General description

The 74LV07AT is a hex buffer with open-drain outputs. The outputs are open-drain and

can be connected to other open-drain outputs to implement active-LOW wired-OR or

active-HIGH wired-AND functions.

Designed to operate over a VCC range from 4.5 V to 5.5 V, the inputs are TTL compatible,

which allows the device to be used to translate from 3.3 V to 5 V.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall

times.

This device is fully specified for partial Power-down applications using IOFF.

The IOFF circuitry disables the output, preventing the damaging backflow current through

the device when it is powered down.

2. Features and benefits

 Direct interface with TTL levels

 Supply voltage range from 4.5 V to 5.5 V

 Typical tPZL of 3.5 ns at 5 V

 Typical VOL(p) < 0.8 V at VCC = 5 V, Tamb = 25 C

 Supports mixed-mode voltage operation on all ports

 IOFF circuitry provides partial Power-down mode operation

 Latch-up performance exceeds 250 mA per JESD 78 Class II

 ESD protection:

 HBM ANSI/ESDA/JEDEC JS-001 Class 2 exceeds 3 kV

 MM JESD22-A115-A exceeds 150 V

 CDM JESD22-C101E exceeds 2 kV

 Specified from 40 C to +85 C and from 40 C to +125 C