Octal D-type flip-flop with reset; positive-edge trigger

General description The 74HC273; 74HCT273 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH c

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PHI

飞利浦

Octal D-type flip-flop with reset; positive-edge trigger

1. General description The 74HC273; 74HCT273 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIG

文件：279.81 Kbytes 页数：17 Pages

NEXPERIA

安世

Octal D-type flip-flop with reset; positive-edge trigger

1. General description The 74HC273-Q100; 74HCT273-Q100 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the

文件：277.13 Kbytes 页数：18 Pages

NEXPERIA

安世

Octal D-type flip-flop with reset; positive-edge trigger

文件：147.06 Kbytes 页数：19 Pages

恩XP

Octal D-type flip-flop with reset; positive-edge trigger

The 74HC273; 74HCT273 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A L • Input levels:• For 74HC273: CMOS level\n• For 74HCT273: TTL level\n\n• Common clock and master reset\n• Eight positive edge-triggered D-type flip-flops\n• Complies with JEDEC standard no. 7A\n• ESD protection:• HBM JESD22-A114F exceeds 2000 V\n• MM JESD22-A115-A exceeds 200 V\n\n• Multiple package;

Nexperia

安世

Octal D-type flip-flop with reset; positive-edge trigger

The 74HC273-Q100; 74HCT273-Q100 is an octal positive-edge triggered D‑type flip‑flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW‑to‑HIGH clock (CP) transition • Automotive product qualification in accordance with AEC-Q100 (Grade 1)• Specified from -40°C to +85°C and from -40°C to +125°C\n\n• Input levels:• For 74HC273-Q100: CMOS level\n• For 74HCT273-Q100: TTL level\n\n• Common clock and master reset\n• Eight positive edge-triggered D-type flip-flops\n• C;

Nexperia

安世

Package：20-TSSOP（0.173"，4.40mm 宽）；包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 功能：主复位 类别：集成电路（IC） 触发器 描述：IC FF D-TYPE SNGL 8BIT 20TSSOP

Nexperia USA Inc.

Package：20-TSSOP（0.173"，4.40mm 宽）；包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 功能：主复位 类别：集成电路（IC） 触发器 描述：IC FF D-TYPE SNGL 8BIT 20TSSOP

Nexperia USA Inc.

Package：20-TSSOP（0.173"，4.40mm 宽）；包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 功能：主复位 类别：集成电路（IC） 触发器 描述：IC FF D-TYPE SNGL 8BIT 20TSSOP

Nexperia USA Inc.