1 General description

The 74HC6323A; 74HCT6323A is an oscillator designed for quartz crystal combined with

a programmable 3-state counter, a 3-state output buffer and an overriding asynchronous

master reset (MR). With the two select inputs S1 and S2 the counter can be switched

in the divide-by-1, 2, 4 or 8 mode. If left floating the clock is divided by 8. The oscillator

is designed to operate either in the fundamental or third overtone mode depending on

the crystal and external components applied. On-chip capacitors minimize external

component count for third overtone crystal applications. The oscillator may be replaced

by an external clock signal at input X1. In this event the other oscillator pin (X2) must

be floating. The counter advances on the negative-going transition of X1. A LOW level

on MR resets the counter, stops the oscillator and sets the output buffer in the 3-state

condition. MR can be left floating since an internal pull-up resistor will make the MR

inactive.

The X1 input has CMOS input switching levels and may be driven by a TTL output using

a pull-up resistor connected to VCC. Inputs include clamp diodes. This enables the use of

current limiting resistors to interface inputs to voltages in excess of VCC.

2 Features and benefits

• Programmable 3-stage ripple counter

• Suitable for over-tone crystal application up to 50 MHz (VCC = 5 V ± 10)

• 3-state output buffer

• Two internal capacitors

• Recommended operating range for use with third overtone crystals 3 to 6 V

• Oscillator stop function (MR)

• Input levels:

– For 74HC6323: CMOS level

– For 74HCT6323: TTL level

• ESD protection:

– HBM JESD22-A114-A exceeds 2000 V

– MM JESD22-A115-A exceeds 200 V

• Specified from -40 °C to +85 °C and from -40 °C to +125 °C

3 Applications

• Control counters

• Timers

• Frequency dividers

• Time-delay circuits

• CIO (Compact Integrated Oscillator)

• Third-overtone crystal operation

74HC6323A属于集成电路（IC） > 计数器，除法器。安世半导体(中国)有限公司制造生产的74HC6323A计数器，除法器计数器和除法器 IC 是数字逻辑器件，可对输入发生的逻辑转换进行计数，然后使用多个并行输出重新发送累加的计数，和/或生成单个输出信号转换，从而对应用某些整数数量输入信号转换进行响应。除了简单的事件计数，它们还可用于各种频率合成应用。