9-bit odd/even parity generator/checker

GENERAL DESCRIPTION The 74HC/HCT280 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Word-length easily expanded by cascading • Similar pin configuration to the “180” for

文件：49.67 Kbytes 页数：7 Pages

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飞利浦

9-bit odd/even parity generator/checker

1. General description The 74HC280; 74HCT280 is a 9-bit parity generator or checker. Both even and odd parity outputs are available. The even parity output (PE) is HIGH when an even number of data inputs (I0 to I8) is HIGH. The odd parity output (PO) is HIGH when an odd number of data inputs ar

文件：245.09 Kbytes 页数：13 Pages

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司

9-bit odd/even parity generator/checker

1. General description The 74HC280; 74HCT280 is a 9-bit parity generator or checker. Both even and odd parity outputs are available. The even parity output (PE) is HIGH when an even number of data inputs (I0 to I8) is HIGH. The odd parity output (PO) is HIGH when an odd number of data inputs ar

文件：245.09 Kbytes 页数：13 Pages

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司

9-bit odd/even parity generator/checker

GENERAL DESCRIPTION The 74HC/HCT280 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Word-length easily expanded by cascading • Similar pin configuration to the “180” for

文件：49.67 Kbytes 页数：7 Pages

PHI

飞利浦

9-bit odd/even parity generator/checker

GENERAL DESCRIPTION The 74HC/HCT280 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Word-length easily expanded by cascading • Similar pin configuration to the “180” for

文件：49.67 Kbytes 页数：7 Pages

PHI

飞利浦

9-bit odd/even parity generator/checker

The 74HC280; 74HCT280 is a 9-bit parity generator or checker. Both even and odd parity outputs are available. The even parity output (PE) is HIGH when an even number of data inputs (I0 to I8) is HIGH. The odd parity output (PO) is HIGH when an odd number of data inputs are HIGH. Expansion to larger • Complies with JEDEC standard no. 7A\n• Input levels:• For 74HC280: CMOS level\n• For 74HCT280: TTL level\n\n• Word-length easily expanded by cascading\n• Generates either odd or even parity for nine data bits\n• ESD protection:• HBM JESD22-A114F exceeds 2000 V\n• MM JESD22-A115-A exceeds 200 V\n\n;

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安世

9-bit odd/even parity generator/checker

The 74HC280-Q100; 74HCT280-Q100 is a 9-bit parity generator or checker. Both even and odd parity outputs are available. The even parity output (PE) is HIGH when an even number of data inputs (I0 to I8) is HIGH. The odd parity output (PO) is HIGH when an odd number of data inputs are HIGH. Expansion

Nexperia

安世

Package：14-SOIC（0.154"，3.90mm 宽）；包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 类别：集成电路（IC） 奇偶校验发生器和校验器 描述：IC PARITY GEN/CHKER 9-BIT 14SO

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司

Package：14-SOIC（0.154"，3.90mm 宽）；包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 类别：集成电路（IC） 奇偶校验发生器和校验器 描述：IC PARITY GEN/CHKER 9-BIT 14SO

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司