Quad bus transceiver; 3-state

ENERAL DESCRIPTION The 74HC/HCT243 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Non-inverting 3-state outputs • 2-way asynchronous data bus communication • Output capabil

文件：49.52 Kbytes 页数：8 Pages

PHI

飞利浦

Quad bus transceiver; 3-state

ENERAL DESCRIPTION The 74HC/HCT243 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Non-inverting 3-state outputs • 2-way asynchronous data bus communication • Output capabil

文件：92.36 Kbytes 页数：17 Pages

PHI

飞利浦

QUAD BUS TRANSCEIVER (3-STATE)

ST

意法半导体

Quad bus transceiver; 3-state

ENERAL DESCRIPTION The 74HC/HCT243 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Non-inverting 3-state outputs • 2-way asynchronous data bus communication • Output capabil

文件：92.36 Kbytes 页数：17 Pages

PHI

飞利浦

Quad bus transceiver; 3-state

ENERAL DESCRIPTION The 74HC/HCT243 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Non-inverting 3-state outputs • 2-way asynchronous data bus communication • Output capabil

文件：92.36 Kbytes 页数：17 Pages

PHI

飞利浦

Quad bus transceiver; 3-state

ENERAL DESCRIPTION The 74HC/HCT243 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Non-inverting 3-state outputs • 2-way asynchronous data bus communication • Output capabil

文件：92.36 Kbytes 页数：17 Pages

PHI

飞利浦